A product built from several dies in one package, from partitioning the system into chiplets through die-to-die interface design, interposer and substrate design, multi-die sign-off and known-good-die test to assembly, final test and package qualification.
Chiplet and advanced packaging lifecycle: 9 stages, 9 gates of its own and 4 hand-offs to the Product lifecycle, from System Partitioning & Package Architecture to Package Qualification & Production Release.
9 stages, 9 gates of its own and 4 hand-offs to the Product lifecycle, 3 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
In collaboration with The Digital Electronics Blog (opens in a new tab)
A dashed sign with a TR tag is a technical readiness review gate.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Deciding how to split the system into dies, which process node each die uses, and which packaging technology joins them, such as a silicon interposer, an embedded bridge, fan-out or 3D stacking.
Multi-die concept approved gate, owned by the Product lifecycle (Concept approval)Partitioning freeze gateTR1, technical readiness review
Defining the links between dies, usually following an open die-to-die standard: protocol, physical layer, lane count, test and repair features, and the bump map both sides and the package share.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
Designing each die through its own SoC or IP style flow, possibly at different nodes or from different suppliers, and verifying the system across die boundaries.
Designing the interposer, bridge or redistribution layers and the package substrate, with power delivery, signal integrity, thermal and warpage analysed together with the dies.
Package design freeze gateDie and package supply agreed gate, owned by the Product lifecycle (Design release)
Checking the whole assembly before release: connectivity and design rules across dies and interposer, timing over the die-to-die links, power, thermal and mechanical stress; then releasing dies and interposer to manufacture.
Testing each die on the wafer to known-good-die quality before assembly, because one faulty die scraps the whole assembled unit, and keeping a bank of tested dies for assembly.
Bumping, attaching and bonding the dies to the interposer or substrate, underfill and encapsulation, usually at an assembly and test supplier.
Testing the assembled unit through its die-to-die links, switching in spare lanes to repair faults where the interface allows, followed by burn-in and system-level test.
Engineering samples gate, owned by the Product lifecycle (Engineering samples)
Qualifying the package for reliability under temperature cycling and other stresses, and ramping assembly and test to volume with supply of every die in place.
Package qualification passed gateTR3, technical readiness reviewProduction release gate, owned by the Product lifecycle (Production release)
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.