Tape-out, Wafer Sort & Known-Good Die

Stages

5. Multi-Die Sign-off^A
6. Tape-out, Wafer Sort & Known-Good Die (this stage)^A
7. Assembly^D

Product milestones

• Die and package supply agreed (SA)

Dies and package milestones

• Package design freeze (PDF)
• Multi-die sign-off (MDS) (technical readiness review TR2)
• Multi-die tape-out (MTO)
• Known-good-die release (KGD)
• First assembled units (FA)

Disciplines

• Multi-die architecture^AO
  • Multi-Die Sign-off: maturity 1.0, Complete. System power and thermal signed off for the whole package against the budget at the multi-die sign-off.
• Die-to-die interface^AA
  • Multi-Die Sign-off: maturity 1.0, Complete. Die-to-die timing met over the final interposer or bridge at the multi-die sign-off.; Die-to-die timing met
  • Tape-out, Wafer Sort & Known-Good Die: maturity Freeze, Frozen. PHY and controller released in the taped-out dies; an interface change now needs every die team and the package team to approve it.
  • Assembly: maturity Freeze, Frozen. PHY and controller released in the taped-out dies; an interface change now needs every die team and the package team to approve it.
• Chiplet die design^A
  • Multi-Die Sign-off: maturity 1.0, Complete. Every die signed off again on its final database with the final package models, and cross-die verification closed on it.^A
  • Tape-out, Wafer Sort & Known-Good Die: maturity Freeze, Frozen. Die databases released and locked; a fix now means a new die revision.; Die databases locked for tape-out
• Multi-die verification^A
  • Multi-Die Sign-off: maturity 1.0, Complete. Cross-die coverage closed and the system verification report agreed at the multi-die sign-off.^A; Cross-die verification signed off
• Interposer and substrate design^DO
  • Multi-Die Sign-off: maturity 1.0, Complete. Assembly-level checks clean or waived across dies, interposer and substrate at the multi-die sign-off.
  • Tape-out, Wafer Sort & Known-Good Die: maturity Freeze, Frozen. Interposer and substrate data released with the dies and locked; a change now needs the die and assembly teams to approve it.; Package design locked for manufacture
• Signal, power and thermal analysis^AAO
  • Multi-Die Sign-off: maturity 1.0, Complete. Signal, power, thermal and stress signed off on the final release set.^A
• Known-good-die test^AO
  • Multi-Die Sign-off: maturity 0.8, Designed. Sort program ready on the signed-off dies, with probe hardware and test limits set, waiting for wafers.
  • Tape-out, Wafer Sort & Known-Good Die: maturity 1.0, Complete. Sort program released and known-good-die quality met, with a bank of tested dies ready for assembly.^A; Known-good-die quality met
• Assembly process^DA
  • Multi-Die Sign-off: maturity 0.5, Feasible. Bumping, attach, bonding and underfill steps proven on test vehicles.
  • Tape-out, Wafer Sort & Known-Good Die: maturity 0.8, Designed. Process, materials and line ready for the first builds with known-good dies.
  • Assembly: maturity 1.0, Complete. First units built and the build reviewed; the assembly process plan is final.^D
• Assembly and test suppliers^AA
  • Multi-Die Sign-off: maturity 0.5, Feasible. Supply agreements in place with every supplier, with quality and change notice terms.
  • Tape-out, Wafer Sort & Known-Good Die: maturity 0.8, Designed. Assembly and test lines set up, with tooling and materials in place for the first builds.
  • Assembly: maturity 1.0, Complete. Lines proven on the first builds, then capacity planned with every supplier for volume.^A
• Final and system-level test^A
  • Multi-Die Sign-off: maturity 0.0, Started. Final and system-level test approach scoped with die test and the assembly supplier: tester and handler platform, load board lead times and test access through the die-to-die links; no test plan yet.
  • Tape-out, Wafer Sort & Known-Good Die: maturity 0.3, Outlined. Final test plan, load boards and burn-in approach outlined from the interface test and repair plan.
  • Assembly: maturity 0.5, Feasible. Final test program first run on the first assembled units, through the die-to-die links.
• Package qualification and reliability^AA
  • Multi-Die Sign-off: maturity 0.0, Started. Qualification needs listed from the package design, the materials and the thermal and warpage results.
  • Tape-out, Wafer Sort & Known-Good Die: maturity 0.3, Outlined. Qualification plan outlined: the standard, the stresses and the sample sizes, agreed with the assembly supplier.
  • Assembly: maturity 0.5, Feasible. Stress boards and hardware ready, with early stress runs on the first assembled units.
• Product, cost and sourcing^AOO
  • Multi-Die Sign-off: maturity 0.8, Designed. Supply agreed with every supplier and the cost model approved; sampling and launch planned with lead customers.
  • Tape-out, Wafer Sort & Known-Good Die: maturity 0.8, Designed. Supply agreed with every supplier and the cost model approved; sampling and launch planned with lead customers.
  • Assembly: maturity 0.8, Designed. Supply agreed with every supplier and the cost model approved; sampling and launch planned with lead customers.