Chip lifecycle / Chiplet lifecycle / Multi-Die Sign-off

Multi-Die Sign-off

Checking the whole assembly before release: connectivity and design rules across dies and interposer, timing over the die-to-die links, power, thermal and mechanical stress; then releasing dies and interposer to manufacture.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^D04 Interposer & Substrate Design

^A05 Multi-Die Sign-offYou are here

^A06 Tape-out, Wafer Sort & Known-Good Die

Product milestones

SADie and package supply agreed

Dies and package milestones

DDCDie design complete PDFPackage design freeze MDSTR2Multi-die sign-off MTOMulti-die tape-out KGDKnown-good-die release

Multi-die architecture^AO

0.8

1.0

Die-to-die interface^AA

1.0

1.0^A

Multi-die verification^A

0.8

1.0^A

Interposer and substrate design^DO

0.8^DO

1.0

Freeze

Signal, power and thermal analysis^AAO

0.8^AA

1.0^A

Known-good-die test^AO

1.0^A

Assembly and test suppliers^AA

0.5

0.8

Final and system-level test^A

0.0

0.3

Package qualification and reliability^AA

0.0

0.3

Product, cost and sourcing^AOO

0.8

Key0.0Started0.3Outlined0.5Feasible0.8Designed1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.You are here: Multi-Die Sign-offAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

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Stages

Product milestones

Die and package supply agreed (SA)

Dies and package milestones

Die design complete (DDC)
Package design freeze (PDF)
Multi-die sign-off (MDS) (technical readiness review TR2)
Multi-die tape-out (MTO)
Known-good-die release (KGD)

Disciplines

Multi-die architecture^AO
- Interposer & Substrate Design: maturity 0.8, Designed. Architecture complete: every die and the package checked against the partitioning and the budgets, with only agreed changes from here.
- Multi-Die Sign-off: maturity 1.0, Complete. System power and thermal signed off for the whole package against the budget at the multi-die sign-off.
Die-to-die interface^AA
- Interposer & Substrate Design: maturity 0.8, Designed. PHY and controller designed and frozen in every die, with the test and repair plan; channel checks with the interposer routing continue.
- Multi-Die Sign-off: maturity 1.0, Complete. Die-to-die timing met over the final interposer or bridge at the multi-die sign-off.; Die-to-die timing met
- Tape-out, Wafer Sort & Known-Good Die: maturity Freeze, Frozen. PHY and controller released in the taped-out dies; an interface change now needs every die team and the package team to approve it.
Chiplet die design^A
- Interposer & Substrate Design: maturity 0.8, Designed. Every die designed, through its own sign-off and frozen; only fixes found by cross-die verification and the multi-die sign-off from here.
- Multi-Die Sign-off: maturity 1.0, Complete. Every die signed off again on its final database with the final package models, and cross-die verification closed on it.^A
- Tape-out, Wafer Sort & Known-Good Die: maturity Freeze, Frozen. Die databases released and locked; a fix now means a new die revision.; Die databases locked for tape-out
Multi-die verification^A
- Interposer & Substrate Design: maturity 0.8, Designed. Cross-die tests running on every frozen die design, with coverage closing.
- Multi-Die Sign-off: maturity 1.0, Complete. Cross-die coverage closed and the system verification report agreed at the multi-die sign-off.^A; Cross-die verification signed off
Interposer and substrate design^DO
- Interposer & Substrate Design: maturity 0.8, Designed. Interposer or bridge and substrate routed, analysed with the dies and frozen; only fixes from the multi-die sign-off from here.^DO
- Multi-Die Sign-off: maturity 1.0, Complete
Signal, power and thermal analysis^AAO
- Interposer & Substrate Design: maturity 0.8, Designed. Signal, power, thermal and warpage analysis on the frozen package and die views meets the targets.^A
Known-good-die test^AO
- Interposer & Substrate Design: maturity 0.5, Feasible. Sort program and probe hardware being developed on the die test patterns.
- Multi-Die Sign-off: maturity 0.8, Designed. Sort program ready on the signed-off dies, with probe hardware and test limits set, waiting for wafers.
- Tape-out, Wafer Sort & Known-Good Die: maturity 1.0, Complete. Sort program released and known-good-die quality met, with a bank of tested dies ready for assembly.^A; Known-good-die quality met
Assembly process^DA
- Interposer & Substrate Design: maturity 0.3, Outlined. Assembly process plan outlined from the frozen interposer and substrate design, with the assembly supplier.
- Multi-Die Sign-off: maturity 0.5, Feasible. Bumping, attach, bonding and underfill steps proven on test vehicles.
- Tape-out, Wafer Sort & Known-Good Die: maturity 0.8, Designed. Process, materials and line ready for the first builds with known-good dies.
Assembly and test suppliers^AA
- Interposer & Substrate Design: maturity 0.5, Feasible. Supply agreements in place with every supplier, with quality and change notice terms.
- Multi-Die Sign-off: maturity 0.5, Feasible. Supply agreements in place with every supplier, with quality and change notice terms.
- Tape-out, Wafer Sort & Known-Good Die: maturity 0.8, Designed. Assembly and test lines set up, with tooling and materials in place for the first builds.
Final and system-level test^A
- Multi-Die Sign-off: maturity 0.0, Started. Final and system-level test approach scoped with die test and the assembly supplier: tester and handler platform, load board lead times and test access through the die-to-die links; no test plan yet.
- Tape-out, Wafer Sort & Known-Good Die: maturity 0.3, Outlined. Final test plan, load boards and burn-in approach outlined from the interface test and repair plan.
Package qualification and reliability^AA
- Multi-Die Sign-off: maturity 0.0, Started. Qualification needs listed from the package design, the materials and the thermal and warpage results.
- Tape-out, Wafer Sort & Known-Good Die: maturity 0.3, Outlined. Qualification plan outlined: the standard, the stresses and the sample sizes, agreed with the assembly supplier.
Product, cost and sourcing^AOO
- Interposer & Substrate Design: maturity 0.8, Designed. Supply agreed with every supplier and the cost model approved; sampling and launch planned with lead customers.
- Multi-Die Sign-off: maturity 0.8, Designed. Supply agreed with every supplier and the cost model approved; sampling and launch planned with lead customers.
- Tape-out, Wafer Sort & Known-Good Die: maturity 0.8, Designed. Supply agreed with every supplier and the cost model approved; sampling and launch planned with lead customers.

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