Yosys

Notes

Created by Claire Wolf and now maintained under the YosysHQ umbrella, it underpins both open ASIC and FPGA toolchains.

Overview

Yosys is an open-source framework for logic synthesis that turns Verilog RTL into a gate-level netlist mapped either to a standard-cell library described in Liberty format or to the primitives of an FPGA. It is driven by scripts made of individual passes, which makes it easy to adapt and has made it the usual synthesis front end of open-source chip and FPGA flows. It is released under the permissive ISC licence and maintained by YosysHQ.

How it works

A typical Yosys script reads the Verilog source, elaborates the design hierarchy from a chosen top module, and converts processes, finite state machines and memories into an internal representation. Optimisation passes then simplify the logic, a technology mapping step converts it to Yosys's own generic cells, and two final steps map it to the target: flip-flops are matched to cells in the Liberty file, and combinational logic is mapped and optimised by ABC, a logic toolbox from the University of California, Berkeley. The result is written out as a Verilog netlist or in other formats such as BLIF or EDIF.

The same framework serves FPGAs. Yosys can map to Xilinx 7-series and Lattice iCE40 and ECP5 devices, and together with the nextpnr place and route tool it gives a fully open flow for some Lattice parts. For ASICs it performs the synthesis stage of the OpenLane and OpenROAD flows, for example on the SkyWater 130 nm open PDK. It also acts as a back end for formal verification tools that check properties and equivalence.

The free version supports synthesisable Verilog-2005; fuller SystemVerilog and VHDL support comes through a commercial edition that adds the Verific front end. For FPGA mapping, the basic abc pass uses a simple unit delay model, while the newer abc9 pass takes cell timing into account and generally maps better.

Examples

• The synthesis stage of the OpenROAD flow scripts, which turns RTL and timing constraints into a netlist for OpenROAD.
• Building a bitstream for a Lattice iCE40 FPGA with Yosys and nextpnr, using no vendor tools.
• Mapping a design to a custom standard-cell library described in a Liberty file with the dfflibmap and abc passes.
• Running formal property checks through a tool that uses Yosys to read and convert the design.

Why it matters

Yosys made it possible to go from RTL to silicon or to an FPGA bitstream with no commercial licences, which matters for education, research, start-ups and open hardware. Logic synthesis engineers, open-source EDA maintainers and open silicon programme teams work with it directly, and designers using open PDKs depend on it.

Related terms

• OpenLane
• OpenROAD
• Logic synthesis
• Liberty
• SKY130

Where it appears on the Hub

Used on 6 pages of the Hub. In each group, the pages that mention it most come first.