Tool · EDA Tools & Flows
OpenLane
An automated open-source RTL-to-GDSII flow that orchestrates Yosys, OpenROAD, Magic, KLayout and netgen into a single configurable pipeline. It was built for open PDKs such as SKY130 and is now in maintenance mode; the project points new designs to its successor, LibreLane.
- Also known as
- OpenLane2, Librelane
- Type
- Tool
- Domain
- EDA Tools & Flows, EDA industry
Notes
Developed by Efabless and used for its chipIgnite shuttle programme, which put open-source flows on real silicon.
Overview
OpenLane is an open-source automated flow that takes a digital design from RTL to a GDSII layout by running a chain of open-source tools, including Yosys, OpenROAD, Magic, Netgen and KLayout, under a single configuration file. It supports the open sky130 and gf180mcu process design kits and can be extended to other PDKs, including proprietary ones. OpenLane is now in maintenance mode, and its maintainers point new projects to LibreLane, its successor.
How it works
OpenLane runs the standard steps of digital implementation in order: synthesis, static timing analysis, floorplanning and input and output placement, global placement with optimisation and detailed placement, clock tree synthesis, power grid generation, diode insertion, routing, writing out the GDS and a final set of reports and checks. The tools behind those steps are Yosys, OpenROAD, which covers floorplanning, placement, clock tree synthesis and routing, Magic, Netgen, CVC, a SPEF extractor and KLayout, together with custom scripts for design exploration and optimisation.
The flow is usually run inside a container, so that every user gets the same tool versions. A small example design, spm, is included to check an installation, and each design is controlled through one configuration file.
OpenLane was created by Efabless and is hosted by The OpenROAD Project under the Apache 2.0 licence. Only its 1.0 releases are supported, and only critical fixes are being merged. LibreLane, based on OpenLane 2, is described as its backwards-compatible successor; it provides Classic and Chip reference flows and can be extended with Python, and its trademarks belong to the FOSSi Foundation.
Examples
- Checking a new installation by running the bundled spm example design through the whole flow.
- Implementing a small digital block on the sky130A PDK and producing a GDSII file with timing and check reports.
- Adding a further PDK, including a proprietary one, by following the documented PDK integration steps.
- Moving an existing project to LibreLane, which keeps backwards compatibility with OpenLane configurations.
Why it matters
OpenLane made a complete RTL-to-GDSII flow available without commercial tool licences, which opened chip implementation to students, researchers, hobbyists and small companies working with open PDKs. Open-source EDA maintainers keep it running, physical design engineers use it to prototype, and open silicon programme managers use it as a common baseline.
Related terms
Part of the EDA Tools & Flows glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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