Term · Test & DFT
Outlier screening
The general practice of using statistical distance rather than absolute specification limits to reject devices that behave unusually compared with their peers, across parametric, spatial or multivariate dimensions.
It targets latent defects that pass conventional tests.
- Also known as
- Outlier detection, Outlier removal
- Type
- Term
- Domain
- Test & DFT, Adaptive test and analytics
Notes
Machine learning methods are increasingly layered on top of classical PAT rules, especially where many correlated measurements exist.
Overview
Outlier screening is the practice of rejecting chips that pass every specification limit but behave unusually compared with similar parts, because such outliers are more likely to carry latent defects that fail later in the field. It replaces fixed pass and fail limits with limits derived from the population being tested, and can look at individual measurements or at how a die compares with its neighbours on the wafer. Part average testing is the best-known form, but the term covers the whole family.
How it works
Parametric methods start from test results such as leakage or supply current. In part average testing, limits are set a number of standard deviations either side of the population mean. Static limits come from data on many earlier lots and are refreshed periodically; dynamic limits are recalculated for each wafer or lot from the parts actually being tested. A part inside the datasheet limits but outside the statistical ones is binned out.
Spatial methods use the wafer map. Defects tend to cluster, so a passing die surrounded by failing ones, the good die in a bad neighbourhood case, carries more risk than an isolated one. Nearest neighbour residual methods compare a die's result with the average of the dies around it, which helps where values drift smoothly across the wafer. Inline methods such as KLA's I-PAT apply the same idea to defect inspection data gathered during fabrication.
Every screen trades reliability against yield. Rejecting parts that would have worked, known as overkill, costs money: a published study on sensor chips found that applying dynamic PAT to all of about 1,500 tests discarded far more good dice than limiting it to tests linked to past field returns. Commentators also report that classic part average and neighbourhood rules are falling short for advanced packages and complex SoCs.
Examples
- Dynamic PAT limits recalculated for every wafer of an automotive microcontroller, rejecting die with unusually high leakage current.
- A good die in a bad neighbourhood rule that removes passing die surrounded by failures on the wafer map.
- KLA's I-PAT summing inline defect inspection results for each die and removing die whose defect counts are outliers.
- Skyworks applying part average testing to high-reliability wireless chips, as reported by the analytics vendor yieldWerx.
Why it matters
Outlier screening is central to automotive and other high-reliability supply chains, and the Automotive Electronics Council first adopted part average testing in 1997. Product engineers, adaptive test engineers and quality teams own the limits and must balance escapes against yield loss, and more fabless companies now run the analysis themselves instead of leaving it to the test house.
Related terms
Part of the Test & DFT glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 19 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
Suggest an improvement
Suggest an improvement to this entry
A clearer definition, an example, a correction or a source an editor can check. Editors review every suggestion before the entry changes.
Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary