Netlist

Notes

The distinction between a behavioural RTL description and a structural netlist is the fundamental boundary that synthesis crosses.

Overview

A netlist is a description of a circuit as a list of components, called instances, and the nets, or wires, that connect their pins. It records what is connected to what, without saying where anything sits on the die. Netlists are the common currency passed between design tools: synthesis produces gate-level netlists for digital logic, and schematics produce transistor-level netlists for analogue and custom circuits.

How it works

A gate-level netlist lists cells from a standard cell library, such as NAND gates and flip-flops, with each pin tied to a named net, and is usually written in a structural subset of Verilog. It comes out of logic synthesis and is modified through physical design, as tools add buffers, clock trees, scan chains and fill. A transistor-level netlist lists individual transistors, resistors and capacitors with their sizes and models, usually in SPICE format, and is generated from a schematic for simulation.

Netlists support most of the checks between design and manufacture. Equivalence checking proves a gate-level netlist matches its RTL. Static timing analysis reads the netlist with cell timing models and extracted wire parasitics. Gate-level simulation runs tests on it. Layout versus schematic extracts a netlist from the layout and compares it with the reference netlist to prove the layout matches the circuit. Parasitic extraction adds resistances and capacitances of the wiring to produce an annotated netlist for timing and simulation.

Formats have varied over the years, including EDIF for exchange between tools, and different tools use their own dialects. Large designs are kept hierarchical, with blocks referenced rather than repeated, so a netlist can describe billions of transistors in manageable files.

Examples

• A gate-level Verilog netlist from synthesis, listing every cell and net in a block.
• A SPICE netlist generated from an analogue schematic for simulation.
• An equivalence check proving the post-layout netlist still matches the RTL after an engineering change order.
• A netlist extracted from layout and compared with the schematic netlist in an LVS run.
• A hard IP block delivered to a customer as a netlist with timing models instead of RTL.

Why it matters

Netlists are handed between RTL, synthesis, physical design, verification and signoff teams many times in a project, and each hand-off must be checked. Physical design and verification engineers read them daily, and IP can be delivered as a netlist rather than RTL when a supplier wants to protect its source.

In the chip lifecycle, the first gate-level netlist appears at synthesis, it evolves through place and route and engineering change orders, and the final netlist is signed off for timing, equivalence and layout versus schematic before tapeout.

It matters most to: Formal Verification Engineer, Gate-Level Simulation Engineer, Logic Synthesis Engineer, Physical Design Engineer, Physical Verification Engineer

Common confusions

Not the same as RTL

RTL describes behaviour at a higher level, which synthesis turns into gates. A netlist lists the actual gates or transistors and their connections. Netlist vs RTL

Not the same as layout

Layout gives the physical shapes and positions on the die. A netlist gives connectivity only.

Not the same as schematic

A schematic is a drawing of a circuit for people to read. The netlist is the text form tools use, often generated from the schematic.

Sources

1. Yosys Open SYnthesis Suite (opens in a new tab), YosysHQ, 2026-10-22
2. Ngspice documentation (opens in a new tab), ngspice project, 2026-10-22
3. IEEE 1800-2023: IEEE Standard for SystemVerilog (opens in a new tab), IEEE Standards Association, 2026-10-22
4. Netlist (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
5. EDIF (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• Verilog netlist
• CDL
• Logic synthesis
• LVS
• SPICE deck

Where it appears on the Hub

Used on 76 pages of the Hub. In each group, the pages that mention it most come first.