Metric · Memory & Storage
Data retention
How long a memory cell keeps the data written to it before the stored charge or state can no longer be read correctly. In DRAM it is short and sets how often cells must be refreshed; in non-volatile memory it is measured in years and is a core part of qualification.
- Also known as
- Retention time, Memory data retention
- Type
- Metric
- Domain
- Memory & Storage, Memory reliability
Overview
Every memory cell slowly loses the state that represents its data. Data retention is the time over which the cell can still be read correctly, under stated conditions of temperature and use. It is one of the main properties a memory cell is designed, tested and qualified for.
How it works
A DRAM cell stores a bit as charge on a small capacitor, and that charge leaks away through the access transistor and the surrounding silicon. The memory must refresh each row before its weakest cells lose their data, so the retention time of those cells sets how often refresh runs and how much power and bandwidth it costs. Leakage rises with temperature, so retention is specified and tested at hot conditions.
A NAND or NOR flash cell stores a bit as charge trapped in or near the transistor gate. The charge escapes over years, faster at high temperature and after the cell has been programmed and erased many times. Retention is therefore tested after cycling, often with high-temperature bakes that speed up the loss, and the results are used to predict retention in the field.
Weak cells are found at wafer test and replaced with spare rows and columns, and error correction covers the few that fail later. The retention a product promises is the result of the cell design, the process, the test screens and the error correction together.
Examples
- Testing DRAM rows at high temperature to find the cells that need the most frequent refresh.
- Baking cycled NAND flash parts to predict how long data will last in the field.
- Choosing stronger error correction because a denser cell has less retention margin.
- Screening out weak cells at wafer test and repairing them with redundant rows.
Why it matters
Retention decides how far a memory cell can be shrunk and how many bits it can hold. Cell and device engineers design for it, memory test engineers screen for it, and reliability engineers qualify it before a product is released. A generation whose retention margin falls short needs a new cell, a new process step or stronger error correction.
It matters most to: Memory Device & Cell Engineer, Memory Product Engineer, Memory Reliability Engineer, Memory Test Engineer
Common confusions
- Not the same as Endurance
- Endurance is how many program and erase cycles a non-volatile cell survives; retention is how long it keeps data once written. Heavy cycling usually shortens retention, so the two are tested together. Data retention vs Endurance
- Not the same as Refresh
- Refresh is the operation that rewrites DRAM rows before they lose data; retention is the property of the cells that decides how often refresh is needed.
Related standards
- JESD47 (stress-test-driven qualification of integrated circuits)
Sources
- Retrospective: An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms (opens in a new tab), arXiv (Onur Mutlu, ETH Zurich), 2026-11-10
- Effect of Radiation Exposure on the Retention of Commercial NAND Flash Memory (opens in a new tab), NASA Goddard Space Flight Center (NASA Technical Reports Server), 2026-11-10
- Memory refresh (opens in a new tab), Wikipedia, 2026-11-10
Related terms
Part of the Memory & Storage glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 4 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary