Roles / Memory Test Engineer

Memory Test Engineer

MEM-008v1

Memory & Storage SiliconTestIC2–IC6Individual contributor

Also known as: Memory ATE Test Engineer; DRAM Test Development Engineer; NAND Test Program Engineer

See this role on the Memory lifecycle or on the SoC lifecycle

Summary

Develops the wafer-sort and final-test programs, patterns and repair flows that screen billions of memory bits per die economically, ensuring every shipped part meets specification while keeping test cost per bit falling.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Lines tagged General are the Hub's general description of this kind of role, used where the role register has no entry yet. They are kept under review and will be refined.

Project

Work done for a product or program.

Develop and maintain wafer-sort, burn-in and final-test programs on memory testers including pattern generation, algorithmic test sequences and datalogging.
Implement memory test algorithms such as March C-, checkerboard, row/column disturb, retention pause and data-bus patterns tuned to known fail mechanisms.
Build the redundancy repair flow — bit-fail map capture, repair solution calculation, fuse blow and post-package repair verification.
Set and validate test limits and guardbands using characterisation distributions and drive limit-change approvals.
Reduce test time and cost per die through parallelism, multi-site test, pattern compression and test-flow re-ordering.
Develop and debug test hardware including probe cards, load boards, DIB design and high-speed signal integrity on the test interface.
Correlate wafer sort to final test to system-level test and resolve test escapes and overkill with product and quality engineering.
Implement built-in self-test and built-in self-repair usage in the test flow with the DFT team.
Support qualification testing, burn-in and high-temperature operating life data collection with the reliability organisation.
Drive test-program release through change control, including correlation data, first-article verification and production readiness signoff.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Maintain test standards, test hardware and program libraries.General
Work with equipment and probe card suppliers on capacity and capability.General
Improve test methods and data tools for future products.General

Major tasks

Project

Produce and hand over the role's key deliverables
- Released wafer-sort and final-test programs with documented test lists
- Redundancy repair flow and fuse-blow recipe
- Test limit and guardband specification with correlation data
- Test time and cost-per-die reduction roadmap
- Probe card, load board and DIB specifications
- Test correlation and production readiness reports
Develop the test solutionGeneral
- Define the test plan and coverage targets
- Write and debug the test program
- Design or specify the test hardware
Release to productionGeneral
- Correlate results across testers and sites
- Optimise test time
- Release the program under change control

Function

Maintain test infrastructureGeneral
- Keep program libraries and standards current
- Plan tester and hardware capacity
Improve methodsGeneral
- Review escapes and adjust coverage
- Develop data analysis tools

Works with

Product engineering
DFT
design teams
assembly and test operations
quality engineering
yield engineering
probe card and OSAT suppliers

Typical backgrounds

BS/MS in Electrical Engineering or Computer Engineering; 2–12 years in memory or SoC test engineering; strong mixed hardware/software aptitude.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

2 / 5

Remote feasibility

Low

Semis core vs. portable

Semis-primary, transfers

Geographic hotspots

Boise (USA), Icheon and Cheongju (Korea), Penang and Muar (Malaysia), Taoyuan and Taichung (Taiwan), Singapore, Xi'an (China), Bengaluru (India)

Certifications / standards training

—

Transfers to (industries)

Transfers to electronics manufacturing test, automotive module end-of-line test and test equipment vendors.

Risk if vacant

Screening quality and test cost both degrade at once, risking DPPM escapes at hyperscale customers and an uncompetitive test cost per gigabit.

Roles / Memory Test Engineer

Memory Test Engineer

MEM-008v1

Memory & Storage SiliconTestIC2–IC6Individual contributor

Also known as: Memory ATE Test Engineer; DRAM Test Development Engineer; NAND Test Program Engineer

See this role on the Memory lifecycle or on the SoC lifecycle

Summary

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Lines tagged General are the Hub's general description of this kind of role, used where the role register has no entry yet. They are kept under review and will be refined.

Project

Work done for a product or program.

Develop and maintain wafer-sort, burn-in and final-test programs on memory testers including pattern generation, algorithmic test sequences and datalogging.
Implement memory test algorithms such as March C-, checkerboard, row/column disturb, retention pause and data-bus patterns tuned to known fail mechanisms.
Build the redundancy repair flow — bit-fail map capture, repair solution calculation, fuse blow and post-package repair verification.
Set and validate test limits and guardbands using characterisation distributions and drive limit-change approvals.
Reduce test time and cost per die through parallelism, multi-site test, pattern compression and test-flow re-ordering.
Develop and debug test hardware including probe cards, load boards, DIB design and high-speed signal integrity on the test interface.
Correlate wafer sort to final test to system-level test and resolve test escapes and overkill with product and quality engineering.
Implement built-in self-test and built-in self-repair usage in the test flow with the DFT team.
Support qualification testing, burn-in and high-temperature operating life data collection with the reliability organisation.
Drive test-program release through change control, including correlation data, first-article verification and production readiness signoff.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Maintain test standards, test hardware and program libraries.General
Work with equipment and probe card suppliers on capacity and capability.General
Improve test methods and data tools for future products.General

Major tasks

Project

Produce and hand over the role's key deliverables
- Released wafer-sort and final-test programs with documented test lists
- Redundancy repair flow and fuse-blow recipe
- Test limit and guardband specification with correlation data
- Test time and cost-per-die reduction roadmap
- Probe card, load board and DIB specifications
- Test correlation and production readiness reports
Develop the test solutionGeneral
- Define the test plan and coverage targets
- Write and debug the test program
- Design or specify the test hardware
Release to productionGeneral
- Correlate results across testers and sites
- Optimise test time
- Release the program under change control

Function

Maintain test infrastructureGeneral
- Keep program libraries and standards current
- Plan tester and hardware capacity
Improve methodsGeneral
- Review escapes and adjust coverage
- Develop data analysis tools

Works with

Product engineering
DFT
design teams
assembly and test operations
quality engineering
yield engineering
probe card and OSAT suppliers

Typical backgrounds

BS/MS in Electrical Engineering or Computer Engineering; 2–12 years in memory or SoC test engineering; strong mixed hardware/software aptitude.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

2 / 5

Remote feasibility

Low

Semis core vs. portable

Semis-primary, transfers

Geographic hotspots

Boise (USA), Icheon and Cheongju (Korea), Penang and Muar (Malaysia), Taoyuan and Taichung (Taiwan), Singapore, Xi'an (China), Bengaluru (India)

Certifications / standards training

—

Transfers to (industries)

Transfers to electronics manufacturing test, automotive module end-of-line test and test equipment vendors.

Risk if vacant

Screening quality and test cost both degrade at once, risking DPPM escapes at hyperscale customers and an uncompetitive test cost per gigabit.

Memory Test Engineer

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

Memory Test Engineer

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

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