Working knowledge of DFT structures and their design implications: scan chains and compression, test points, ATPG fault models, boundary scan (IEEE 1149.1), BIST for memory and logic, and the timing, area and power cost each imposes on a block.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: DFT exposure in a design role or a DFT rotation; anchored in ATPG/scan insertion tool flows and the IEEE 1149.1/1687 standards.
Register version 1.