Your LinkedIn feed doesn't know what a guard ring is.
The Hub's community does.
Technical news, candid talk with people who do the same work, everyday tools and roles that fit your discipline. Post under a handle if you would rather not use your name.
Your path through the Hub
Four steps for industry professionals, from the first links to follow to what is new on the Hub today.
Where to start
- Read the news →
Sourced, sector-specific coverage.
- Join a board →
Ask people who have solved it.
- Browse roles →
Filter by discipline and seniority.
- Use the tools →
Calculators, the MPW calendar and datasheet tools.
Training plan. From your own discipline to the whole chip programme: outcomes, modules, exercises and self-checks built on the Hub's lifecycles.
In the Industry Review 2026
- Chapter 3: Process technology and the PDK roadmap
- Chapter 4: Advanced packaging and chiplets
- Chapter 5: AI accelerators and compute demand
- Chapter 6: Memory
- Chapter 7: Power and compound semiconductors
- Chapter 9: Talent and workforce
- Chapter 12: Design and EDA, including AI-assisted design
Other chapters (6)
The whole review: analysis, cited facts and live Hub data, chapter by chapter.
Lifecycles for you
The chip lifecycles that the training plan for Industry professionals draws on most. Each one sets out its stages, the gates that check them and the work handed over.
- SoC and full-chip lifecycle →The whole chip, from its specification through IP integration, full-chip design and verification, tape-out, bring-up and qualification to production and end of life.15 stages, 22 gates
- Product lifecycle →The business lifecycle of a semiconductor product, from the first sign of a market opportunity through concept, definition, development, validation, sampling, qualification, launch, ramp, maturity and decline to end of life and the support that continues after the last shipment. The engineering lifecycles run inside it.13 stages, 31 gates
- Soft IP lifecycle →One reusable block delivered as synthesisable design code (soft IP), made in-house or taken in from a supplier, from its specification through design, verification, implementation views and quality checks to a versioned release for SoC teams.8 stages, 10 gates
- Test program and ATE development lifecycle →The manufacturing test of a chip, from the test strategy and DFT alignment while the chip is specified, through the test plan, probe cards, load boards and sockets, pattern generation and conversion and a test program built before silicon, to first silicon debug and correlation, characterisation and limit setting, test time reduction and release to production, then yield and test data monitoring, maintenance and end of life.12 stages, 20 gates
- Firmware and software stack lifecycle →The software that ships with a chip, from the boot ROM in its masks to the drivers, SDK and updates customers rely on: requirements and the hardware-software interface, development on virtual platforms and emulation before silicon, boot ROM freeze, firmware, drivers and board support, security, signing and secure update, SDKs and toolchains, bring-up on first silicon, validation, production release, and maintenance and vulnerability response until the end of support.12 stages, 17 gates
New to the lifecycle? Start here: the lifecycle in five steps, see the whole lifecycle on one page or look up a term in the glossary.
What changes for you
Industry news is spread across trade press, vendor sites and paywalls.
One place, sourced, with the company and topic pages behind every story.
You cannot talk pay, a PDK or an OSAT openly under your own name.
Ask under a handle that still shows you are who you say you are.
A certificate is a claim with no proof.
A badge with a public page that shows its live status, so anyone can check it in seconds.
What the Hub brings
Built for people who already work in chips and want straight answers, from peers they can trust.
Industry news you can check
Sourced coverage across design, manufacturing, packaging, EDA, equipment and policy. Companies named in a story link to their profile, and each profile lists its recent coverage.
A map of roles and skills
Role pages show responsibilities, KPIs, skills and tools. Skill pages show live demand counted from Hub listings, and half-life. Compare up to three roles side by side, with every figure tied to its source.
Ask with credentials, not your name
Post under a pseudonymous handle that shows only the verified traits you choose, for example discipline and region. No name and no employer, so you can talk pay or a PDK openly.
Peer discussion that rewards help
Community boards for questions and answers. An accepted answer earns the author Chips, a reputation currency that cannot be bought.
Jobs in your sector, alerts included
Every listing is a chips role. Filter by discipline, level and remote policy, save searches as daily email alerts, and see open roles ranked by fit to your profile.
Tools for daily engineering questions
Die per wafer, yield, package cost, unit conversion and more. The tools run in the browser and need only a free account.
Credibility anyone can verify
Verify with a work email and your profile earns a Hub Verified badge. Anyone can check it on a public page, and you can embed it in a signature or a profile.
Experts and a route back
Book a free intro chat or a paid deep-dive with an approved expert. Between roles, the Comeback Track lists you by verified expertise, and never asks why.
Your data is yours
Export or delete your account any time. Forum posts are anonymised on deletion, not left with your name.
No ad trackers
Analytics use no third-party advertising trackers.
Chips are earned, never bought
You earn Chips by helping other members. They cannot be bought.
Live on the Hub for industry professionals
Ordered by what is most useful to you first. Sign in and opt in to personalization and it also reorders around your discipline and activity. Sign in
Open roles
6The newest open roles from companies on the Hub: what the market wants for your discipline, for when you are ready to move.
See all →
SiTime · Process / DeviceSiTime · Analog / Mixed-Signal
Ambiq Micro · Test
Astera Labs · PackagingAstera Labs · TestAmbiq Micro · Analog / Mixed-SignalNews
6Latest coverage across the industry on technology and company moves, without digging through a general feed.
See all →Upcoming events
4Upcoming conferences and meetups. Plan where to learn, present and meet peers in your field.
See all →Community
5Recently active discussion threads where engineers trade practical answers: get unstuck, share what you know and build your reputation.
See all →Courses
0Published courses with level, hours and price shown up front, for upskilling in a specific area and keeping your skills current.
See all →Work in progress. Nothing here for this audience yet. Suggest a course or contribute content.
Experience briefs
0Short-term, skill-building work from real teams. Try a new area or pick up project experience alongside your job.
See all →Work in progress. Nothing here for this audience yet. Suggest a brief or contribute content.
Directory highlights
0Verified company profiles for researching a prospective employer, supplier or partner before you apply, pitch or reach out.
See all →Work in progress. Nothing here for this audience yet. Add a company or contribute content.
Research
0Work in progress. Nothing here for this audience yet. Suggest research or contribute content.
Funding & M&A
0Recent funding rounds and acquisitions, showing which companies are growing and where hiring momentum may follow.
See all →Work in progress. Nothing here for this audience yet. Suggest a deal or contribute content.
Grants & incentives
0Work in progress. Nothing here for this audience yet. Suggest a programme or contribute content.
Target markets
0Work in progress. Nothing here for this audience yet. Suggest content or contribute content.
Academic institutions
0Work in progress. Nothing here for this audience yet. Suggest an institution or contribute content.
Join for free
Read everything. Ask anything. Build a profile only when you want to.