The Semiconductor Hub Industry Review 2026

Contents

1. 1. Market and demand by end market

   Not yet audited: draft for review

   Chips are sold into end markets that grow for different reasons and at different speeds. This chapter maps demand across data centre and AI, smartphones, PCs and other compute clients, automotive, industrial and energy, communications infrastructure, consumer electronics and the connected edge. It separates growth in units from growth in chip content per unit, explains why the industry swings between shortage and glut through inventory, lead times and memory prices, and shows which markets carry the growth in the forecasts it cites. It closes with a practical method for reading whole-industry forecasts as dated vintages with stated scope and assumptions, and with the live Hub data worth watching.

2. 2. Capacity, fabs and siting

   Not yet audited: draft for review

   Wafer capacity is the physical limit on how many chips the industry can make, and it is being rebuilt on a new map. This chapter explains where new fabs are going and why, how leading-edge and mature capacity differ in cost, customers and risk, and how capacity is measured, from installed wafer starts and utilisation to the much larger total of plans that may never be built. It sets out what decides a fab site, from power, water and skills to supply chain security, sustainability and subsidies, then follows a fab from business case through construction, tool move-in and ramp, and explains why schedules slip. It closes with the economics of clusters, the payback logic behind public incentives, equipment orders as the earliest signal of real capacity, the risk of overbuild and what to watch.

3. 3. Process technology and the PDK roadmap

   Not yet audited: draft for review

   A process node is a manufacturing recipe, a set of design rules and a commercial offer, not a measurement. This chapter explains what a node name does and does not tell a designer, how the leading edge is changing with gate-all-around transistors, backside power delivery and new lithography, and why mature and specialty processes for analogue, RF, power, embedded memory and FD-SOI keep their place. It sets out why the cost of a transistor and the cost of a design no longer fall together, what a process design kit contains and how its maturity versions shape a schedule, and how teams choose a node and a foundry on performance, cost, IP, capacity, second sourcing and supply risk. It closes with shuttles for startups and universities, the link from process scaling to system scaling through chiplets and packaging, and what to watch.

4. 4. Advanced packaging and chiplets

   Free sampleNot yet audited: draft for review

   The package has moved from the last and cheapest step of making a chip to the place where the performance of AI hardware is decided. This chapter traces packaging from wire bond and flip chip through wafer-level and fan-out to 2.5D interposers and 3D stacks joined by hybrid bonding, explains why large designs are being split into chiplets, and looks at the hard parts: die-to-die links, memory beside the processor, heat, power delivery and the known good die. It reads the Hub's live data on 2.5D packaging capacity and accelerator build, explains how a new package is developed with a supplier and why that choice is hard to undo, and closes with what to watch.

5. 5. AI accelerators and compute demand

   Not yet audited: draft for review

   Demand for AI compute has become the single strongest pull on the leading edge of the industry, and it lands on far more than the accelerator chip. This chapter follows that demand from the uses that create it, through the different needs of training and inference, into the AI server and its parts, the choice between general-purpose GPUs and custom chips, the memory wall, the links within and between servers, rack power, liquid cooling and electricity. It reads the Hub's live data on rental prices, the price of throughput, server and rack costs, token prices and industrial power, explains how to read each one, and closes with what the whole system asks of silicon, packaging and memory supply and what to watch.

6. 6. Memory

   Not yet audited: draft for review

   Memory is the part of the industry where AI demand meets commodity economics. This chapter explains DRAM, HBM and NAND as businesses and as technologies, why memory swings harder than any other part of the cycle, how the memory wall made stacked HBM the scarcest part of AI hardware, and how that pull on wafers reaches conventional DRAM, storage and every buyer of a phone, a PC or a server. It then turns to the few makers who supply almost all of it, what a JEDEC generation change means for buyers, how to read spot and contract prices, how long-term agreements and allocation work, and what buyers, designers and investors should watch.

7. 7. Power and compound semiconductors

   Not yet audited: draft for review

   Power semiconductors decide how much energy is lost each time electricity is converted, and it is converted several times between the grid and the load. This chapter compares silicon MOSFETs and IGBTs with silicon carbide and gallium nitride, follows them into electric vehicles, industry, energy and data centres, and explains the silicon carbide supply chain: crystal growth, defects, larger wafers, vertical integration, a market led by a few suppliers, carmaker sourcing and the shift to local supply in China. It closes with gallium nitride's foundry model, power packaging and automotive qualification, and what to watch.

8. 8. Supply chain, chokepoints and geopolitics

   Not yet audited: draft for review

   The chip value chain is global by design: each step sits where the skills, suppliers and customers for it gathered over decades. That spread is a strength in normal times and a weakness when a single region, a single tool or a single material becomes a point of failure. This chapter maps how design, IP and EDA, equipment, materials, wafer fabrication and assembly and test are spread across regions and where they are concentrated, then examines the chokepoints that matter most. It explains how export controls on advanced computing and chipmaking equipment work and how the targets of those controls have responded, compares the industrial policies of the United States, Europe, Japan and others, and sets out the resilience strategies a company can adopt, from dual sourcing and buffers to design for a second source and compliance screening. It closes with lead times as a stress indicator and what to watch.

9. 9. Talent and workforce

   Not yet audited: draft for review

   Every fab announced and every chip programme funded is also a hiring plan, and the industry is writing more of them than its talent pipeline can fill. This chapter looks at where the engineer shortfall is deepest and why new fabs and design programmes sharpen it, which roles and skills are in demand and which remain scarce, how an ageing workforce and competition from software employers drain experience, how far the industry still is from drawing on its whole talent pool, and which pathways, from universities to technician programmes and reskilling, can close the gap. It ends with a guide to reading job-market data, since a posting is not a hire, and with the signals worth watching.

10. 10. Funding, venture and M&A

    Not yet audited: draft for review

    Chip companies need patient capital, and they need it long before they have a customer. This chapter explains why even a company that owns no fab spends heavily on design, masks, IP, tools and test before its first sale, and why design wins and qualification make the road to revenue so long. It follows the funding stages from grants and university spinouts through seed, venture and strategic investors to public markets, sets out what investors look for at each gate, and describes the non-dilutive money, shuttle programmes, incubators and accelerators that stretch a young company's runway. It compares the main revenue models, looks at mergers and acquisitions as a way to buy talent, IP, scale and market access, with the integration and review risks they carry, and closes with how the industry cycle moves funding and what to watch.

11. 11. Sustainability and emissions

    Not yet audited: draft for review

    A chip's climate footprint is spread across the whole value chain, and much of it sits outside the fab that makes it. This chapter explains where a fab's emissions come from: process gases released on site, the electricity it buys, and the larger body of upstream emissions in the materials, wafers, chemicals, gases, spare parts, capital goods and transport it depends on, together with the electricity chips draw once they are in use, which AI data centres are pushing up. It explains why upstream emissions gather in a short list of suppliers, why polysilicon and wafer making are so energy hungry, and what energy sourcing, water and ultrapure water mean for a site. It sets out the levers that work, from abatement and renewable power purchase to supplier engagement, energy-efficient design and equipment reuse, and shows how to read a sustainability disclosure without being misled. It explains why the Hub describes and does not score companies, outlines reporting obligations in general terms and closes with what to watch.

12. 12. Design and EDA, including AI-assisted design

    Not yet audited: draft for review

    A chip is designed and checked long before any wafer is made, and the quality of that work decides whether first silicon works. This chapter follows the design flow from architecture and specification through RTL, verification, synthesis, physical design and sign-off to tape-out and validation of real silicon. It explains why verification takes the largest share of effort, why tools, process kits and IP are bound so tightly together, and where open standards, open instruction sets and open-source tools fit. It covers security and functional safety as design disciplines, multi-die design and system technology co-optimisation, the place of firmware and hardware and software decoupling, and the rising cost of design. It then sets out where AI-assisted design helps today, the risks it brings for correctness, confidentiality, licensing and tool qualification, and how teams adopt it in stages. Evidence on design productivity is scarce, and the chapter says so where it matters.

13. 13. Outlook and what to watch

    Not yet audited: draft for review

    The earlier chapters of this review each end with what to watch. This closing chapter draws those threads into the handful of open questions that will decide the next few years for the industry: whether AI demand keeps compounding or pauses to digest, whether packaging and memory keep pace with logic, whether new regional fabs fill, how export controls and localisation reshape the market, whether the talent gap closes, how electrification and energy pressure play out, and whether AI-assisted design lifts productivity. Each question is set out with the forces pulling either way and the signals that would answer it. The chapter then explains how to read forecasts as dated vintages, maps a watch list to the Hub's live data and pages, sets out scenario thinking without invented probabilities and describes how readers can contribute data to sharpen the next edition.