Process technology and the PDK roadmap

Key takeaways

• A node name is a generation label, not a dimension. Compare processes on the figures a foundry supplies for density, speed, leakage and cost, measured on the cells and blocks a design will really use.
• The leading edge now advances through new transistor and wiring structures, gate-all-around devices and backside power, as much as through finer patterning, and each gain in density, power or speed is traded against the others.
• Mature and specialty processes are not legacy. Analogue, RF, power, embedded memory and FD-SOI products depend on device options and long support lives that the leading edge does not offer.
• The cost of each transistor no longer falls reliably with each node, while the cost of designing a chip at the leading edge keeps rising. That pushes teams to put on the newest process only the parts of a system that gain from it.
• A process design kit is the contract between fab and designer. Its maturity, from early access to production, decides how much of a design may need rework, so a schedule should be built around the kit's release plan.
• Choosing a node and a foundry is a business decision as much as a technical one: performance, wafer and design cost, IP availability, capacity, a second source and export and supply risk all weigh in.
• Shuttles and multi-project wafers let startups, universities and product teams prove silicon at a fraction of a full mask set, and the shuttle calendar often sets the real tape-out date.