Measuring how much of the intended chip behaviour a verification test suite has actually exercised, using a list of features and situations that must be seen at least once.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: Verification courses, SystemVerilog covergroups, and closing coverage on real block or chip projects.
Register version 1.