Also known as: Senior Staff Verification Engineer; Principal Verification Engineer; Technical Lead, SoC Verification; DV Technical Lead
See this role on the SoC lifecycle or on the Soft IP lifecycle
Leads the technical plan and sign-off for chip-level verification across a multi-engineer team.
Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction
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