Also known as: DDR Controller Verification Engineer; Memory Subsystem Verification Engineer; HBM and LPDDR Verification Engineer
See this role on the SoC lifecycle or on the Soft IP lifecycle
Verifies memory controllers and PHY interfaces so DDR, LPDDR and HBM traffic is correct, fast and compliant.
Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction
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