A testing method where a tool generates random inputs within set rules, so many unexpected cases are tried against a chip design, with coverage showing what was hit.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: SystemVerilog and UVM courses, writing random tests for small blocks, and coverage closure on real projects.
Register version 1.