The manufacturing test of a chip, from the test strategy and DFT alignment while the chip is specified, through the test plan, probe cards, load boards and sockets, pattern generation and conversion and a test program built before silicon, to first silicon debug and correlation, characterisation and limit setting, test time reduction and release to production, then yield and test data monitoring, maintenance and end of life.
Test program and ATE development lifecycle: 12 stages, 18 gates of its own and 2 hand-offs to the Product lifecycle, from Test Strategy & DFT Alignment to Test End of Life.
12 stages, 18 gates of its own and 2 hand-offs to the Product lifecycle. Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
In collaboration with The Digital Electronics Blog (opens in a new tab)
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Deciding how the product will be tested in manufacturing while the design can still change: the outgoing quality and test cost targets, which insertions (wafer sort, final test, burn-in, system-level test) screen which defects, the class of automatic test equipment, and the design-for-test features the chip must carry, such as scan, compression, memory BIST, boundary scan, IEEE 1500 wrappers and IEEE 1687 instruments, agreed with the DFT architects.
Test concept approval gate, owned by the Product lifecycle (Concept approval)DFT architecture aligned gate
Turning the strategy into a test plan and a test specification: every datasheet parameter, fault model and screen mapped to a test, an insertion and its conditions, with the test flow and binning plan, the coverage matrix, the test hardware specification, and the tester and handler capacity the plan needs.
Designing, building and checking out the hardware that connects the tester to the part: probe cards for wafer sort, load boards and sockets for final test, change kits for handlers, and burn-in and system-level test boards where the plan uses them, with signal and power integrity analysis of the tester interface and a checkout before silicon arrives.
Generating the structural test patterns with automatic test pattern generation (stuck-at, transition and, where the plan asks, cell-aware and path delay patterns), adding memory BIST, boundary scan and instrument access patterns, capturing functional patterns from verification, converting all of them to the tester's format and simulating them against the netlist with tester timing.
Writing the test program before silicon exists: the test flow, test methods, levels, timing sets, pattern bursts, limits tables, bins and datalog setup, built in the tester's development environment, checked offline against the specification, and run where possible on the real tester and hardware with a loopback or reference part so that first silicon is not the first test of the program.
Putting first wafers and packaged parts on the tester: bringing up the program, debugging patterns and test methods, diagnosing scan failures, and correlating tester results with the bench, with simulation, between testers and between wafer sort and final test, until the program is trusted enough to screen engineering samples.
First silicon on the tester gateCorrelation complete gateEngineering test release gate
Measuring how the parts behave across process corners, supply voltage and temperature, with shmoo plots and parametric distributions from corner lots, then setting production test limits and guard bands from the data and the datasheet, and releasing the program used to test the qualification lots.
Bringing test time and cost down to the target without losing quality: more sites in parallel, concurrent test of independent blocks, pattern reordering and compaction, removing or sampling tests that the data shows never fail, adaptive test rules, and fewer or shorter insertions such as reduced burn-in, each change justified with data and reviewed for its quality risk.
Moving the program and its hardware into production at the internal test floor or the test subcontractor: capability studies of repeatability and reproducibility across testers and hardware sets, correlation between sites, operator instructions, the test quality sign-off and a formal release under change control.
Watching the test data as volume ramps: yield and bin trends by lot, wafer and site, statistical bin limits and alarms, outlier screening, tester and hardware health, excursion response with holds and dispositions, and feedback of failure signatures to design, the fab and assembly.
Volume test ramp gate, owned by the Product lifecycle (Volume ramp)Yield baseline established gate
Keeping the program right for the life of the product: changes for new tester software, new hardware sets, die revisions, process and assembly changes and second sources, continued test cost reduction, hardware maintenance and spares, and analysis of test escapes and customer returns, each change released under change control and, where it affects customers, notified to them.
Closing the test side of a product at its end of life: tester and hardware capacity for the last-time buy, spare hardware for the final builds, the last test runs, and an archive of the program, patterns, hardware design data and test data kept for the retention period agreed with customers, before hardware is retired.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.