Chip lifecycle / Test program lifecycle / Characterisation & Limit Setting

Characterisation & Limit Setting

Measuring how the parts behave across process corners, supply voltage and temperature, with shmoo plots and parametric distributions from corner lots, then setting production test limits and guard bands from the data and the datasheet, and releasing the program used to test the qualification lots.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^A06 First Silicon Debug & Correlation

^A07 Characterisation & Limit SettingYou are here

^O08 Test Time & Cost Optimisation

Product, test cost and quality milestones

Test engineering milestones

TPRTest program ready for silicon FSFirst silicon on the tester CCCorrelation complete EREngineering test release LFTest limits freeze QRQualification test release TTTest time target met

Test program management and cost^A

0.8

DFT architecture and test access^A

1.0

Test planning and specification^D

0.8

1.0

Freeze

ATPG and pattern generation^D

1.0^A

Pattern conversion and simulation^D

1.0

Test program development^D

1.0^A

Probe card engineering^A

1.0

Load boards, sockets and handlers^A

1.0

Analog, mixed-signal and RF test^A

1.0

Characterisation and limits^A

0.8

1.0^A

Freeze^D

Product engineering and yield^D

1.0^A

Test data and adaptive test^OO

0.5

0.8

Burn-in and system-level test^A

0.8

1.0

ATE platform and test operations^A

0.5

0.8

Test quality and escapes^O

0.5

0.8

Key0.0Planned0.3Early draft0.5Draft0.8Feature complete1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateYou are here: Characterisation & Limit SettingAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

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Stages

First Silicon Debug & Correlation^A
Characterisation & Limit Setting (this stage)^A
Test Time & Cost Optimisation^O

Product, test cost and quality milestones

Test engineering milestones

Disciplines

Test program management and cost^A
- First Silicon Debug & Correlation: maturity 0.8, Feature complete. Engineering and qualification test releases run, with the cost model and the capacity plan on measured test times.
- Characterisation & Limit Setting: maturity 0.8, Feature complete. Engineering and qualification test releases run, with the cost model and the capacity plan on measured test times.
- Test Time & Cost Optimisation: maturity 0.8, Feature complete. Engineering and qualification test releases run, with the cost model and the capacity plan on measured test times.
DFT architecture and test access^A
- First Silicon Debug & Correlation: maturity 1.0, Complete. Scan, compression, BIST and instruments proven on first silicon, with the findings fed back to design and the next product.
Test planning and specification^D
- First Silicon Debug & Correlation: maturity 0.8, Feature complete. Specification matches the program built for silicon: every test coded with draft limits, the flow and binning plan complete; updated with first silicon findings.
- Characterisation & Limit Setting: maturity 1.0, Complete. Production limits from characterisation in the specification and the coverage matrix final at the limits freeze.
- Test Time & Cost Optimisation: maturity Freeze, Frozen. Specification and coverage matrix under change control: a removed or sampled test needs its data, a quality review and approval.
ATPG and pattern generation^D
- First Silicon Debug & Correlation: maturity 1.0, Complete. Patterns proven on first silicon with scan diagnosis working; compaction and reordering for test time follow.^A
- Characterisation & Limit Setting: maturity 1.0, Complete. Patterns proven on first silicon with scan diagnosis working; compaction and reordering for test time follow.
- Test Time & Cost Optimisation: maturity 1.0, Complete. Patterns proven on first silicon with scan diagnosis working; compaction and reordering for test time follow.
Pattern conversion and simulation^D
- First Silicon Debug & Correlation: maturity 1.0, Complete. Converted patterns passing on first silicon, with the fixes found in debug folded in.
Test program development^D
- First Silicon Debug & Correlation: maturity 1.0, Complete. Released for its stage: correlated and released for engineering samples, then for qualification lots with limits from characterisation, then multi-site at the test time target.^A
- Characterisation & Limit Setting: maturity 1.0, Complete. Released for its stage: correlated and released for engineering samples, then for qualification lots with limits from characterisation, then multi-site at the test time target.
- Test Time & Cost Optimisation: maturity 1.0, Complete. Released for its stage: correlated and released for engineering samples, then for qualification lots with limits from characterisation, then multi-site at the test time target.
Probe card engineering^A
- First Silicon Debug & Correlation: maturity 1.0, Complete. Probe card proven on first wafers, tuned for contact and signal quality; production sets follow.
- Characterisation & Limit Setting: maturity 1.0, Complete. Probe card proven on first wafers, tuned for contact and signal quality; production sets follow.
- Test Time & Cost Optimisation: maturity 1.0, Complete. Probe card proven on first wafers, tuned for contact and signal quality; production sets follow.
Load boards, sockets and handlers^A
- First Silicon Debug & Correlation: maturity 1.0, Complete. Load boards and sockets proven on first packaged parts and correlated; production sets follow.
- Characterisation & Limit Setting: maturity 1.0, Complete. Load boards and sockets proven on first packaged parts and correlated; production sets follow.
- Test Time & Cost Optimisation: maturity 1.0, Complete. Load boards and sockets proven on first packaged parts and correlated; production sets follow.
Analog, mixed-signal and RF test^A
- First Silicon Debug & Correlation: maturity 1.0, Complete. Bench to tester correlation done on first silicon; trim and calibration settings from characterisation follow.
- Characterisation & Limit Setting: maturity 1.0, Complete. Bench to tester correlation done on first silicon; trim and calibration settings from characterisation follow.
Characterisation and limits^A
- First Silicon Debug & Correlation: maturity 0.8, Feature complete. Early characterisation data from first silicon, with the correlation results to set guard bands against.
- Characterisation & Limit Setting: maturity 1.0, Complete. Characterisation complete across corners, voltage and temperature, with production limits and guard bands set at the limits freeze.^A; Test limits baselined (milestone for one item)
- Test Time & Cost Optimisation: maturity Freeze, Frozen. Test limits and guard bands under change control; the test removal analysis is done against the frozen limits.
Product engineering and yield^D
- First Silicon Debug & Correlation: maturity 1.0, Complete. Correlation signed off: tester, bench, simulation and other testers agree, so yield learning, the yield model and the yield baseline run on trusted data.^A
- Characterisation & Limit Setting: maturity 1.0, Complete. Correlation signed off: tester, bench, simulation and other testers agree, so yield learning, the yield model and the yield baseline run on trusted data.
- Test Time & Cost Optimisation: maturity 1.0, Complete. Correlation signed off: tester, bench, simulation and other testers agree, so yield learning, the yield model and the yield baseline run on trusted data.
Test data and adaptive test^OO
- First Silicon Debug & Correlation: maturity 0.5, Draft. Datalogs and failure capture working with the program, and data from first silicon flowing to product engineering.
- Characterisation & Limit Setting: maturity 0.8, Feature complete. Outlier screening and adaptive test rules drafted from characterisation data and the test removal analysis.
- Test Time & Cost Optimisation: maturity 0.8, Feature complete. Outlier screening and adaptive test rules drafted from characterisation data and the test removal analysis.^O
Burn-in and system-level test^A
- First Silicon Debug & Correlation: maturity 0.8, Feature complete. Burn-in and system-level test content ready and run on the boards before silicon, then on first parts.
- Characterisation & Limit Setting: maturity 1.0, Complete. Burn-in recipe released for the qualification lots, with the system-level test content proven; reductions follow.
- Test Time & Cost Optimisation: maturity 1.0, Complete. Burn-in recipe released for the qualification lots, with the system-level test content proven; reductions follow.^A
ATE platform and test operations^A
- First Silicon Debug & Correlation: maturity 0.5, Draft. Tester time, debug stations and data collection ready for the program build, first silicon and engineering samples.
- Characterisation & Limit Setting: maturity 0.8, Feature complete. Production test sites and capacity prepared, with qualification lots run at the site and the transfer package drafted.
- Test Time & Cost Optimisation: maturity 0.8, Feature complete. Production test sites and capacity prepared, with qualification lots run at the site and the transfer package drafted.
Test quality and escapes^O
- First Silicon Debug & Correlation: maturity 0.5, Draft. Coverage and screening risks reviewed on the program before silicon and on the engineering release before samples ship.
- Characterisation & Limit Setting: maturity 0.8, Feature complete. Qualification release reviewed, with known gaps, outlier screens and proposed test removals assessed for escape risk.
- Test Time & Cost Optimisation: maturity 0.8, Feature complete. Qualification release reviewed, with known gaps, outlier screens and proposed test removals assessed for escape risk.

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