1. Purpose and scope
This stage produces the first working design code of the block: the synthesisable description of its main function, its interfaces and enough of its configuration logic for an integrator to replace the placeholder shell. It runs from the micro-architecture review to the early access release, which places the design at the Alpha step of the IP maturity scale: main features are in, good enough for early integration trials only.
The aim is a drop that an integrator can rely on for what it claims, not a finished block. Interfaces, clocks, resets, power control and test access come first, because the SoC depends on them before secondary functions. Static checks and trial synthesis run from the first drop so that problems stay small, and the release notes state every gap.
Completing the remaining features and configuration options, driving the static checks to clean and freezing the code happen in the next stage, RTL Completion. Layout of a hardened macro is not soft IP work; it belongs to the hard IP lifecycle.
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