A memory product, from the density and generation roadmap and the choice of cell and array through the process built around the cell, array test chips and yield learning, design and verification of the die, first silicon and characterisation, stacking for HBM and packaging, qualification to JEDEC methods and with system makers, to the high-volume ramp, binning and grading, cost-down shrinks and end of life.
Memory product lifecycle (DRAM, NAND and HBM): 14 stages, 12 gates of its own and 10 hand-offs to the Product lifecycle, from Density & Generation Roadmap to End of Life.
14 stages, 12 gates of its own and 10 hand-offs to the Product lifecycle, 3 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
In collaboration with The Digital Electronics Blog (opens in a new tab)
A dashed sign with a TR tag is a technical readiness review gate.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Deciding which memory generations, densities, interface standards and product families to build next, for DRAM, NAND and HBM, from system makers' needs, the progress of JEDEC standards, the bit cost each option can reach and the capacity the company can bring to it, and approving a generation for definition.
Generation roadmap approval gate, owned by the Product lifecycle (Opportunity accepted)Generation definition approved gate, owned by the Product lifecycle (Concept approval)
Choosing the storage cell and how cells are organised: for DRAM the capacitor and access transistor structure, the bit line and word line scheme and the array to periphery split; for NAND the cell type, bits per cell, layer count direction and the array under or beside the periphery; with bank, page and plane organisation, redundancy and error correction budget, die size and bits per wafer estimated for each option.
Cell and array concept selected gateTR1, technical readiness reviewProduct plan agreed gate, owned by the Product lifecycle (Plan approval and development commit)
Developing the process the memory node needs: cell patterning, capacitor or channel hole and stack formation, isolation, peripheral transistors and interconnect, tuned for the cell together, and freezing a memory process baseline with the design rules and device models the product design is built on.
Running test vehicles with full or partial arrays, cell monitors and defect structures on the memory baseline, testing them for retention, disturb, endurance and fail bit maps, and driving defect density and cell spread down until the array yields on a trend that supports a product die.
Designing and verifying the product die: the array and its sense amplifiers, decoders and repair, the periphery, voltage generators and control logic, the interface to the JEDEC standard chosen, test modes and on-die error correction, with circuit simulation across corners on extracted layout, behavioural model and interface verification and, for HBM, the base die interface and stack design, through to the design verification sign-off on the complete layout.
Finishing the verified die and releasing it to mask making: full-chip assembly of the array tiles, periphery and interface, physical verification against the rules and the schematics, electromigration, IR drop and electrostatic discharge checks, re-verification of late engineering changes, spare logic and metal fix provision, the core and base die databases of a stack checked against the frozen stack design, and the tape-out checklist, through to the mask order.
Bringing up the first product wafers: wafer test and repair flows, functional and timing checks against the specification, characterisation across voltage, temperature and speed, debug of marginal circuits and early fixes, and the first engineering samples to lead customers with a preliminary datasheet and models.
First silicon gateEngineering samples gate, owned by the Product lifecycle (Engineering samples)
Turning tested dies into packaged products: known good die test, through-silicon vias, thinning, die stacking and bonding for HBM and stacked DRAM or NAND packages, stack test and repair, thermal and warpage control, and the package or stack handed to system makers and to the package and chiplet teams who integrate HBM beside a processor.
Qualifying the component to published JEDEC reliability and environmental test methods and to the target application: data retention, endurance for NAND, operating life, temperature and humidity stress, package and stack reliability, and electrical compliance with the standard, recorded in a qualification report.
Qualifying the part with system makers: compatibility and validation on their processor and controller platforms, interface training and timing margin, thermal and power behaviour in the system, and each customer's own reliability and quality checks, until the part is approved for their products.
Sorting tested parts into speed, power, temperature and density grades and deciding how partly good dies and stacks are used, set up before the production release so each orderable part has a grade behind it, then steering the product mix and inventory across grades, densities and package options through volume production to match demand and price.
Releasing the part to production and ramping wafer starts, test and assembly capacity, holding the process and the test flow in control, raising yield and good bits per wafer to their mature level, and meeting committed allocations to customers.
Production release gate, owned by the Product lifecycle (Production release)Ramp complete gate, owned by the Product lifecycle (Ramp complete)
Lowering cost per bit once the product is in volume: shrinking the die on an improved process, moving NAND to more layers or bits per cell, adding densities, speed grades or package options, each change requalified and notified to customers under change control.
Shrink or derivative approval gate, owned by the Product lifecycle (Lifecycle review)Shrink tape-out gateShrink qualified and notified gate, owned by the Product lifecycle (Product change notice)
Withdrawing a memory product in an orderly way as demand moves to newer generations: notifying customers, taking last-time orders, running final wafer starts and builds, managing die bank and inventory to the end, and archiving the product and test record.
Discontinuance notice gate, owned by the Product lifecycle (Discontinuance notice)Last wafer start gate, owned by the Product lifecycle (Last-time ship)
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
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