1. Purpose and scope
The cell is the defining choice of a memory generation. It fixes how small a bit can be, how the process must be built, how the array is sensed and how the part behaves over time: how long a DRAM cell holds its charge, how much a NAND cell can be programmed and erased, how neighbouring cells disturb one another. This stage chooses the cell and the array around it, with enough evidence that the generation can reach its density and its cell behaviour targets.
The array organisation is chosen at the same time: banks and bank groups, page size, planes for NAND, data width, where the periphery sits, and how much redundancy and error correction the array will need. These choices set die size and bits per wafer, which in turn decide cost per bit and whether the business case holds. That is why the stage closes with two gates together: Cell and array concept selected on the technology track and Product plan agreed on the business track.
In scope: candidate cells and their simulation, early short-loop structures, sensing studies, organisation and periphery placement options, die size and bit cost estimates, and the first redundancy and correction budget. Out of scope: developing the process modules to capability, which belongs to Memory Process Technology, and detailed circuit design, which belongs to Die Design & Verification.
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