Closes Cell & Array Architecture by confirming exit criteria, work products, reviews, decisions and hand-offs before its gate. Owned by the stage lead.
MustThe cell and array concept is recorded with its evidence and the rejected options.
MustCell device simulation results show retention, disturb and, for NAND, endurance margins against target, or a plan to close the gap.
MustThe die size and bit cost estimate falls within the range the business case assumes, or the gap is stated.
MustThe array and periphery architecture is drafted, with organisation and periphery placement chosen.
MustThe product target specification is final and baselined.
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