Use when the macro is signed off and its test chip is about to be assembled and checked. Run by the Hard IP design engineer with the physical verification engineer and the foundry interface manager.
MustHard macro sign-off is passed and the GDS layout is released.
MustThe test chip specification is final and reviewed by design, validation and reliability.
MustThe slot on the shared wafer run is confirmed, with the date the database is due.
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