Chip lifecycle / Checklists / Structured ASIC lifecycle / FPGA Prototype Conversion: entry checklist

FPGA Prototype Conversion: entry checklist

For the start of converting an FPGA prototype once the customer design is accepted. The FPGA-to-ASIC conversion engineer runs it. Designs that arrive as RTL skip this stage.

1. Inputs

MustThe customer design is accepted and the statement of work is signed.
Evidence
Customer design accepted decision record
Owner
Custom silicon programme manager
MustThe prototype version to convert is frozen, and the customer agrees changes after this point are change requests.
Evidence
Prototype baseline record
Owner
Customer ASIC architect
SeeFlow: Engineering change request and impact assessment
MustThe primitive inventory lists every FPGA specific primitive the design uses.
Evidence
Primitive inventory
Owner
FPGA-to-ASIC conversion engineer

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