Confirms every primitive is mapped, the converted design is shown equivalent to the prototype and the customer has agreed it, before the converted design baseline agreed gate. The FPGA-to-ASIC conversion engineer owns it.
MustEvery FPGA primitive is mapped or redesigned, and the mapping is reviewed by a second engineer.
MustClock managers and global networks are mapped onto the base clock generators and spines, and clock domain crossing checks are clean or waived.
MustBehaviour that relied on the FPGA is listed and handled, such as register start-up values and memory contents loaded with the configuration.
These differences pass equivalence checks against the prototype netlist and still change behaviour at power up.
MustTest logic for the converted design is planned from the platform test architecture.
22 more items for registered members.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.