Process · Fab Ops, Yield & Metrology
Overlay metrology
The measurement of misalignment between a newly patterned layer and the layer beneath it, using dedicated targets and reported as overlay error in nanometres across the wafer and field.
- Also known as
- Registration metrology
- Type
- Process
- Domain
- Fab Ops, Yield & Metrology, Metrology
Notes
Image-based and diffraction-based overlay coexist, with DBO favoured at the tightest nodes for its precision.
Overview
Overlay metrology is the measurement of how accurately each newly patterned layer on a wafer lines up with the layers already beneath it, reported as overlay error in nanometres at many points across the wafer and within each exposure field. Its results decide whether a lithography layer is accepted or reworked, and they are fed back to the scanner to correct the wafers that follow. At advanced nodes the allowed error is only a few nanometres, so the measurement must be far more precise than that.
How it works
Most overlay is measured on purpose-built targets in the scribe lines between chips. In image-based overlay, a microscope images a target with features on both layers, traditionally a box inside a box or bars inside bars, and software compares their centres. In diffraction-based overlay, also called scatterometry, the target is a pair of stacked gratings, and any shift between them changes the light they diffract. Diffraction-based methods are fast and increasingly used for complex layers, but they are sensitive to asymmetries that processing can introduce into the target, so target design matters. Targets have shrunk from about 25 micrometres across to a few micrometres.
Timing matters as well. Measuring after develop, while the pattern is still in resist, allows a misaligned layer to be stripped and reprinted. Measuring after etch shows the final result, including shifts caused by etch, and is used more in memory, but by then rework is no longer possible. After-etch overlay on real device structures can be measured with SEMs or with optical tools that read in-device features.
The data feed control loops. Fabs measure selected wafers per lot at chosen sites, fit the errors to models covering translation, rotation and higher-order distortions, and send corrections to the scanner. A calibrated offset between target and device overlay is included, and scanner sensor data can be used to predict overlay and reduce the number of measurements needed.
Examples
- Image-based overlay on box-in-box or bar-in-bar targets right after a lithography step, so a misaligned layer can be stripped and reprinted.
- Diffraction-based overlay on stacked grating targets measured with an ASML YieldStar system.
- Post-etch overlay measured on in-device features with an optical tool instead of a slower SEM.
- Denser overlay sampling on 3D NAND channel-hole layers to capture shifts caused by etch.
- Higher-order corrections computed from one lot's overlay data and sent to the scanner for the next lot.
Related terms
- Overlay
- Run-to-run control
- Alignment
- Scanner
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