Tool · EDA Tools & Flows
Fusion Compiler
Synopsys's single-binary RTL-to-GDSII implementation tool, which runs synthesis, placement, clock tree synthesis, routing and signoff-accurate analysis on one unified data model.
It targets the convergence problems that arise when handing designs between separate tools.
- Also known as
- FC
- Type
- Tool
- Domain
- EDA Tools & Flows, Logic synthesis
Notes
Launched in 2018 as the successor flow to the Design Compiler plus IC Compiler II handoff model.
Overview
Fusion Compiler is Synopsys's RTL-to-GDSII implementation tool, which takes a digital design from RTL through synthesis, placement, clock tree synthesis and routing to a finished layout within one product. Synopsys built it on a single data model shared by its synthesis and place and route engines, with signoff-based timing, parasitic extraction and power analysis built in. The aim is fewer surprises when a design moves from synthesis to layout, a common cause of extra iterations when separate tools are used.
How it works
In a traditional flow, a synthesis tool such as Design Compiler produces a netlist that is passed to a separate place and route tool such as IC Compiler II, each with its own view of timing and wiring. Fusion Compiler, announced in November 2018, combined a new high-capacity synthesis technology with IC Compiler II's place and route technology on one scalable data model. Because both stages share the same database and analysis, synthesis can take more account of physical effects, and Synopsys presented the result as more predictable quality of results.
Synopsys describes the tool's analysis as based on its golden signoff technology, so that the timing and parasitics seen during implementation sit closer to what the separate signoff tools will later report. Machine learning is used within the flow, and the product page pairs the tool with DSO.ai, which searches flow settings automatically.
The tool became generally available in 2019, and by December 2021 Synopsys reported more than 500 customer tapeouts on processes from 40 nm to 3 nm. These are the vendor's own figures. Moving to a single tool also means reworking scripts, checks and handoffs written for separate synthesis and layout tools.
Examples
- Renesas deploying Fusion Compiler across its automotive design teams after evaluating it on production designs, announced in March 2019.
- Synopsys's December 2021 report of more than 500 customer tapeouts with Fusion Compiler on nodes from 40 nm to 3 nm.
- A block team running Fusion Compiler with DSO.ai to search flow settings for better power, performance and area.
- An implementation flow that replaces separate Design Compiler and IC Compiler II runs with one Fusion Compiler session working on a single database.
Why it matters
Physical design engineers, synthesis engineers and CAD methodology teams in companies that use Synopsys implementation tools work in Fusion Compiler daily, and the choice of implementation tool shapes a project's scripts, compute needs and achievable power, performance and area.
In the chip lifecycle, Fusion Compiler is used from early synthesis and floorplan exploration through block and top-level implementation to the routed layout handed to signoff and tapeout, and for engineering change orders after that.
It matters most to: CAD / Design Methodology Engineer, EDA Physical Implementation Applications Engineer, Physical Design Engineer, Physical Design Methodology Engineer, RTL Synthesis Engineer
Common confusions
- Not the same as Design Compiler
- Design Compiler is Synopsys's long-established synthesis tool, whose netlist goes on to a separate place and route step. Fusion Compiler covers synthesis and implementation in one product. Fusion Compiler vs Design Compiler
- Not the same as IC Compiler II
- IC Compiler II is Synopsys's place and route tool. Its technology forms the implementation side of Fusion Compiler, but it remains a separate product. Fusion Compiler vs IC Compiler II
- Not the same as a software compiler
- Despite the name, Fusion Compiler turns hardware descriptions into chip layout, not programs into machine code.
Sources
- Fusion Compiler: RTL-to-GDSII Design Solution (opens in a new tab), Synopsys, 2026-10-22
- IC Compiler II: Place & Route Solution (opens in a new tab), Synopsys, 2026-10-22
- Design Compiler: Timing, Area, Power, & Test Optimization (opens in a new tab), Synopsys, 2026-10-22
- Synopsys Unveils Fusion Compiler, Enabling 20 Percent Higher Quality-of-Results and 2X Faster Time-to-Results (press release, 6 November 2018) (opens in a new tab), Synopsys, 2026-10-22
- Synopsys' Fusion Compiler Enables Renesas to Accelerate Delivery of Next-Generation Automotive Designs (press release, 14 March 2019) (opens in a new tab), Synopsys, 2026-10-22
- Synopsys Extends Industry Leadership as Customers Surpass 500 Tapeouts Using Flagship Fusion Compiler Solution (press release, 2 December 2021) (opens in a new tab), Synopsys, 2026-10-22
Related terms
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