Tool · EDA Tools & Flows
IC Compiler II
Synopsys's place and route tool for digital implementation, built on a compact in-memory data model for large flat designs. It performs placement, clock tree synthesis, routing and timing closure.
Synopsys also offers Fusion Compiler, which combines synthesis and place and route in one tool.
- Also known as
- ICC2
- Type
- Tool
- Domain
- EDA Tools & Flows, EDA industry
Notes
Its NDM library format replaced Milkyway and consolidated logical, physical and timing views into a single library file.
Overview
IC Compiler II is Synopsys's place and route tool for digital chip implementation, which takes a synthesised netlist with its constraints and produces a placed, clocked and routed layout. Synopsys introduced it in 2014 as a rebuilt successor to its original IC Compiler, with a new multithreaded infrastructure intended for very large designs. Synopsys now also offers Fusion Compiler, which combines synthesis and implementation in a single product.
How it works
The tool covers the main implementation steps. It plans the floorplan, either flat or hierarchically, places standard cells and macros with congestion-aware optimisation, builds the clock tree, routes the design with rules for advanced nodes, and runs optimisation loops to close timing, power and area. Synopsys's description lists flat and hierarchical design planning, early design exploration, clock tree synthesis, routing convergence, manufacturing compliance and signoff closure among its features.
Its data model combines library and design data in one compact structure. For design planning, it automatically builds outline models of the logical hierarchy, so engineers can explore a large chip at top level without loading every detail, while the hierarchy itself is kept intact. When it launched, Synopsys said the new infrastructure could handle designs with more than 500 million instances and reused proven engines from IC Compiler, such as its placer and the Zroute router, while keeping industry-standard input and output formats.
Later releases added what Synopsys calls Fusion technologies, which bring signoff engines into the implementation loop: PrimeTime delay calculation, path-based timing analysis, IR-drop-driven optimisation and signoff engineering change orders. Synopsys also describes machine learning-driven optimisation. Performance and quality claims for the tool come from Synopsys and should be read as vendor statements.
Examples
- A block-level implementation of a processor core in IC Compiler II, followed by timing signoff in PrimeTime.
- Hierarchical design planning of a large SoC to compare several floorplans before committing to one.
- A team that moved from IC Compiler to IC Compiler II at its own pace, as Synopsys continued to support the older tool after 2014.
- A project that adopted Fusion Compiler to run synthesis and place and route on a single data model.
Why it matters
Place and route decides whether a digital design meets its frequency, power and area targets and how long it takes to get there. Physical design engineers run IC Compiler II day to day, CAD and methodology teams build flows around it, and EDA application engineers support customers moving between tool generations.
Related terms
Part of the EDA Tools & Flows glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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