Process · EDA Tools & Flows
Gate sizing
The selection of a cell's drive strength and threshold-voltage flavour from the available library variants to trade delay against area, leakage and switching power.
It is applied continuously through synthesis, optimisation and timing ECOs.
- Also known as
- Sizing, Cell swapping
- Type
- Process
- Domain
- EDA Tools & Flows, Logic synthesis
Notes
Leakage recovery, swapping fast low-Vt cells back to high-Vt on non-critical paths, is a standard late-flow power saving.
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