Calibre

Notes

Calibre is the clearest example of a tool whose market position comes from foundry deck availability rather than from the tool alone.

Overview

Calibre is Siemens EDA's physical verification platform, used to check that chip layouts obey the foundry's design rules, match their schematics, and are ready for manufacturing. Its tools cover design rule checking, layout versus schematic, parasitic extraction, design for manufacturing and mask data preparation. Many foundries supply signoff rule decks for Calibre, which has made it a common reference tool for tapeout.

How it works

Calibre was developed by Mentor Graphics, which Siemens acquired in 2017; the tools are now part of Siemens' EDA business. The platform reads layouts in standard formats such as GDSII and OASIS and runs rule decks written in its own rule language. Calibre nmDRC checks geometric rules, Calibre nmLVS extracts devices and connectivity from layout and compares them with the schematic or netlist, and further tools check electrical rules, extract parasitic resistance and capacitance for timing and simulation, and run design for manufacturing analysis such as lithography hotspot detection and smart fill.

Its engines are built for size. They exploit the hierarchy of a design, so repeated cells are checked once, and spread work across many processors, which lets full-chip checks on billions of shapes finish overnight. Results appear in a viewer that links each violation to the layout editor, whether that is a custom layout tool or a place and route system, so designers can fix errors in place.

Beyond design, Calibre tools are used in mask data preparation and computational lithography, including optical proximity correction, the step that reshapes layout so it prints as intended on the wafer. That links the same platform to both the designer's signoff and the mask shop's work.

Examples

• A full-chip Calibre nmDRC run against the foundry's signoff deck the night before tapeout.
• Calibre nmLVS finding a short between two nets in an analogue block.
• Parasitic extraction for post-layout simulation of a high-speed interface.
• Lithography hotspot checks flagging a layout pattern that may not print reliably.
• Optical proximity correction applied to layout data in the mask shop.

Why it matters

Physical verification engineers, layout engineers and CAD teams run Calibre daily in the final stages of a design, and many foundries supply rule decks for it, so a design team's tapeout schedule often depends on Calibre runs. Mask data preparation and computational lithography engineers use other parts of the platform.

Related terms

• Siemens EDA
• DRC
• LVS
• PEX
• DRM

Where it appears on the Hub

Used on 53 pages of the Hub. In each group, the pages that mention it most come first.