Die-to-die

Notes

Parallel forwarded-clock schemes dominate on short advanced-package links while serial schemes are used when the substrate is organic and longer.

Overview

A die-to-die interface carries data between separate silicon dies inside one package, over an organic substrate, a silicon interposer or a bridge, using much less energy and with much lower delay than a link between separate packages. It is what lets several chiplets behave like one large chip, and it is increasingly built to open standards such as UCIe.

How it works

Inside a package, dies sit millimetres apart, so links can use many short, simple connections instead of the long, heavily equalised serial links needed across a circuit board. Two styles are common. Parallel interfaces use many wires, each at a moderate data rate, which suits advanced packages with fine-pitch bumps such as silicon interposers and bridges. Serial interfaces use fewer, faster lanes, which suits standard organic packages with coarser bump pitch.

A die-to-die interface has layers like other links: a physical layer of transmitters, receivers and clocking; an adapter for link training, error detection and retry; and a protocol layer that carries traffic such as PCI Express, CXL or a company's own on-chip protocol, so that software sees the dies as one system. Key figures of merit are bandwidth per millimetre of die edge, energy per bit and latency.

Standards help dies from different sources work together. UCIe, from the UCIe Consortium, and Bunch of Wires, from the Open Compute Project, define open die-to-die interfaces, while some companies use proprietary links between their own dies.

Examples

• A server processor whose compute dies connect to an I/O die over a die-to-die link on an organic substrate.
• An AI accelerator using a parallel die-to-die interface across a silicon interposer to reach high bandwidth.
• A licensed UCIe PHY placed along the edge of a chiplet.
• A test chip used to characterise a die-to-die interface's bandwidth and signal margins.

Why it matters

As large chips are split into chiplets to improve yield, reuse IP and mix process nodes, the die-to-die interface becomes critical to performance, power and cost. Die-to-die interface architects and IP designers, chiplet architects, packaging engineers and verification engineers work on it, and its area and power overhead must be paid on every die.

In the chip lifecycle die-to-die choices are made at architecture, together with the package, implemented and verified during design, and characterised on test chips and first silicon.

Related terms

• UCIe
• Chiplet
• Bump pitch
• Interposer

Where it appears on the Hub

Used on 35 pages of the Hub. In each group, the pages that mention it most come first.