3D-IC and Chiplet DFT Engineer

Project

Work done for a product or program.

• Implement IEEE 1838 die wrapper registers and test access ports for stacked dies.
• Plan test flow across known-good-die, partial stack and final package insertions.
• Design die-to-die interface test, loopback and lane repair for UCIe and HBM links.
• Define through-silicon via and micro-bump test strategy.
• Coordinate test access with base die, interposer and memory stack partners.
• Model test cost and yield loss from each insertion for package decisions.
• Support multi-die bring-up and diagnose interconnect failures.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Maintain the policies, processes and tools of the function.General
• Keep the function compliant with legal, financial and regulatory requirements.General
• Report the function's performance and improve it over time.General

Project

1. Produce and hand over the role's key deliverables
   • 3D DFT architecture specification
   • IEEE 1838 wrapper RTL
   • Die-to-die test plan
   • Multi-insertion test cost model
2. Support programsGeneral
   • Agree what each program needs
   • Deliver in time for milestones
3. Manage issuesGeneral
   • Track requests to closure
   • Escalate risks

Function

1. Run the functionGeneral
   • Maintain policies and processes
   • Keep records and controls
2. ImproveGeneral
   • Report performance
   • Lead improvement work