Die-to-die interface

Notes

Energy per bit, usually quoted in picojoules, is the headline figure by which competing die-to-die schemes are compared.

Overview

A die-to-die interface is the circuitry and protocol that carry data between two or more silicon dies inside the same package, such as the chiplets of a multi-die processor. Because the dies sit only millimetres apart, the link can use many simple wires and spend far less energy per bit than a link that leaves the package. It is the building block that lets one large design be split into chiplets that still behave like a single chip.

How it works

Most die-to-die interfaces are wide and parallel. Each module or slice drives a group of data wires at a moderate rate with a forwarded clock, and because the channel is short and loses little signal, the circuits can stay simple. Compared with a SerDes this needs more wires, but the lower rate per wire allows single-ended signalling and dense wiring. Serial alternatives, built like very short-reach SerDes, also exist.

UCIe defines a complete stack in three layers. The physical layer holds the electrical front end, a sideband channel for exchanging parameters, and logic for initialisation, training, calibration, test and repair. A die-to-die adapter manages the link, negotiates the protocol and can add CRC checking and retry. The protocol layer maps PCI Express, CXL or a streaming mode for user-defined traffic. A standard package variant suits organic substrates with coarser bumps and longer reach; an advanced package variant suits silicon bridges or interposers, with finer bumps, more lanes per module and spare lanes for repair.

The Open Compute Project's Bunch of Wires (BoW) is a simpler open PHY built from 16-bit unidirectional slices, usable on laminate or advanced packaging. Across all options the trade-offs are bandwidth per millimetre of die edge, energy per bit, latency and how much package technology the link demands.

Examples

• A UCIe link on a standard organic package using 16 transmit and 16 receive lanes per module at a bump pitch of about 110 micrometres.
• A UCIe link on an advanced package with 64 lanes per module, spare lanes for repair and a bump pitch of about 45 micrometres.
• A Bunch of Wires interface, which OCP says several companies use on process nodes from 65 nm to 5 nm.
• A 3D die stack using UCIe-3D, which UCIe 2.0 added for hybrid bonding at bump pitches down to about 1 micrometre.

Why it matters

Chiplet and die-to-die architects choose the interface and the split between dies, IP designers build the PHY and adapter, package engineers design the short channels between bumps, and verification and test engineers prove that links from different vendors interoperate and can be repaired.

In the chip lifecycle, the interface is chosen at architecture during partitioning, designed and verified with the package in mind, tested on each die before assembly and again across the assembled link, and brought up during system validation.

It matters most to: Chiplet Integration Architect, Die-to-Die and UCIe Verification Engineer, Die-to-Die Interface Architect, Die-to-Die Interface IP Design Engineer, Die-to-Die Package Interconnect Engineer

Common confusions

Not the same as an off-package SerDes

Board and cable links cross lossy channels many centimetres long, so they use fast serial lanes with heavy equalisation. Die-to-die links cross millimetres and favour many slower wires.

Not the same as a chiplet

A chiplet is the die itself. The die-to-die interface is the link circuitry and protocol it uses to talk to its neighbours.

Not the same as an interposer

An interposer or bridge carries the wires between dies. The interface is the transmitter, receiver and protocol logic at each end of those wires.

Related standards

• UCIe (Universal Chiplet Interconnect Express die-to-die interconnect specification)

Key figures

• About 0.3 pJ/bit on advanced packages and 0.5 pJ/bit on standard packages Energy efficiency quoted for UCIe 1.0 links in a 2022 Synopsys technical article. (Source: Unpacking the Rise of Multi-Die SoCs with UCIe (Manuel Mota, 17 July 2022), 2026-10-22)

Sources

1. Specifications (opens in a new tab), UCIe Consortium, 2026-10-22
2. Unpacking the Rise of Multi-Die SoCs with UCIe (Manuel Mota, 17 July 2022) (opens in a new tab), Synopsys, 2026-10-22
3. Bunch of Wires PHY Specification (release candidate, WG approved 20 May 2022) (opens in a new tab), Open Compute Project, 2026-10-22
4. Open Compute Project Foundation Announces a Proven SoC Disaggregation Interface Specification (press release, 19 July 2022) (opens in a new tab), Open Compute Project, 2026-10-22

Related terms

• UCIe
• BoW
• Disaggregation
• Chiplet

Where it appears on the Hub

Used on 12 pages of the Hub. In each group, the pages that mention it most come first.