BLR (Board Level Reliability)

Notes

Particularly demanding for WLCSP and large body BGAs in mobile products, where drop performance often sets the design limit.

Overview

BLR (board level reliability) is the testing of how well the solder joints between a packaged chip and its printed circuit board survive the stresses of use, such as repeated temperature swings, drops, flexing and vibration. The part is soldered to a standard test board and stressed until joints fail, so the results describe the package, solder and board working together rather than the silicon alone. It is a standard qualification step for ball grid arrays and wafer level chip scale packages, especially in handheld products.

How it works

Silicon, package materials and circuit boards expand by different amounts when they heat up, so every temperature swing strains the solder joints between them, and repeated swings eventually crack them through fatigue. Drops send shock through the board and flexing bends it; both load the joints mechanically and can also crack fragile layers inside the chip itself, an effect known as chip board interaction.

JEDEC standardises the main tests. Temperature cycling (JESD22-A104) covers both components and their solder interconnections in air or another gas. The board level drop test (JESD22-B111) fixes the test board and method so that drop performance of surface-mounted components can be compared reproducibly, and the cyclic bend test (JESD22-B113) evaluates components for handheld products under repeated bending. During testing the joints are commonly monitored electrically, so that a crack shows up as a break or flicker in resistance, and failed samples are cross-sectioned to find where the crack ran.

Results depend on more than the package. Die size and thickness, solder ball alloy, board pad design and copper thickness all matter: Texas Instruments, for example, recommends pads not defined by solder mask and thinner copper to keep joints taller, and gives rules for underfill when customers use it. That is why BLR results are always tied to a stated board and assembly process.

Examples

• Texas Instruments qualifying its DSBGA wafer chip scale packages with board level thermal cycling and drop tests, designed to need no underfill in intended applications.
• Amkor's study of a large 22 nm FD-SOI wafer level package, testing chip board interaction under drop and temperature cycling on board for different die thicknesses and ball alloys.
• Board level drop testing to JESD22-B111, which fixes the test board and method so that results from different suppliers can be compared.
• Cyclic bend testing to JESD22-B113, used to compare surface-mount ICs intended for handheld products under repeated board bending.

Related terms

• Solder ball
• Temperature cycling
• WLCSP
• Warpage
• Drop test
• Solder fatigue

Where it appears on the Hub

Used on 8 pages of the Hub. In each group, the pages that mention it most come first.