A new fabless company's first chip, from the problem and market thesis and the founding team through a proof of concept in simulation and on an FPGA prototype, pre-seed and seed funding, architecture and partner selection, and a test chip on a shuttle, to evaluation with design partners, a Series A and product silicon, qualification and first revenue, and scale-up. Funding gates sit beside the engineering gates.
Fabless startup chip lifecycle: 15 stages and 27 gates, from Problem & Market Thesis to Scale-up.
15 stages and 27 gates, 3 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
In collaboration with The Digital Electronics Blog (opens in a new tab)
A dashed sign with a TR tag is a technical readiness review gate.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Stating the problem a new chip could solve better than what exists today, who has it and why now, and testing that thesis with potential customers, technical experts and public market data before a company is formed or money is raised.
Bringing together founders who between them cover the technical, product and business work of the first years, agreeing roles, equity and decision rights, forming the company and assigning the founders' relevant inventions to it.
Showing that the core technical claim holds: first in an algorithm or architecture model run in simulation, then in a working prototype on an FPGA board or emulator running representative workloads, with the results measured against the thesis.
Raising the early money that pays for the team, the tools and the first silicon.
Turning the prototype into a chip architecture and choosing the partners the company will depend on: the foundry and process node for first silicon, the EDA licensing model and compute, third-party IP, design services, packaging and test, with agreements signed before test chip design starts.
Designing a test chip that proves the riskiest parts of the architecture on silicon, writing and verifying its RTL with the licensed IP integrated, and running every RTL drop through the implementation flow, often with a design services partner, until the test chip RTL is frozen for sign-off.
Closing verification on the frozen test chip RTL, closing timing, power, physical verification and the foundry's checks for the shuttle, checking the RTL on the prototype platform, confirming the shuttle slot and preparing the board, package and lab plan for when silicon returns.
Releasing the signed-off test chip database to the multi-project wafer shuttle or small dedicated run, then packaging and bringing up the test chip on a lab board, measuring it against the model and against the claims made to investors and customers, and recording what has to change for product silicon.
Test chip tape-out gateTest chip validated gateTR1, technical readiness review
Putting the test chip, or an evaluation platform built around it, in the hands of one or more design partners under an evaluation or joint development agreement, so real customers confirm the value, sharpen the requirements and state their intent to buy.
Raising the round that pays for product silicon, on the evidence of test chip and design partner results, while the product requirements and specification, the node and package for production, the cost targets and the plan to first revenue are fixed.
Designing and verifying the full product chip on the production process: fixing the test chip blocks from the silicon lessons, integrating licensed IP, writing and verifying the product RTL and running implementation trials, until the product RTL is frozen for sign-off.
Closing verification on the frozen product RTL, closing timing, power and test on the production process, passing physical verification and the foundry's checks, and preparing the package, boards, software and the full mask set order for the product tape-out.
Releasing the signed-off product database and ordering the full mask set, then bringing up first product silicon with its firmware and software, validating it against the specification, writing the errata, and shipping engineering samples and evaluation kits to design partners and first customers.
Product tape-out gateTR2, technical readiness reviewProduct first silicon gateProduct silicon validated gateEngineering samples gate
Qualifying the product for its target market, releasing production test and the outsourced supply chain, turning design partner commitments into purchase orders, and shipping the first production units for revenue.
Qualification passed gateTR3, technical readiness reviewProduction release gateFirst revenue gate
Growing from one product and a few customers into a company that ships reliably: raising growth funding, building sales, support and operations, securing supply and second sources, planning derivatives and the next product, and keeping quality and cost under control as volume rises.
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