Chip lifecycle / Startup lifecycle / Evaluation with Design Partners

Evaluation with Design Partners

Putting the test chip, or an evaluation platform built around it, in the hands of one or more design partners under an evaluation or joint development agreement, so real customers confirm the value, sharpen the requirements and state their intent to buy.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^A08 Test Chip Tape-out, Bring-up & Evaluation

^A09 Evaluation with Design PartnersYou are here

^A10 Series A & Product Definition

Company, funding and customers milestones

DPSDesign partner signed PVDesign partner validation SASeries A closed

Engineering milestones

TCSTest chip sign-off TTTest chip tape-out TVTR1Test chip validated PSFProduct specification freeze

Founders and company strategy^O

0.5

0.8

Customers and design partners^A

0.8

1.0

Funding and finance^A

0.5

0.8

Legal, IP and agreements^A

0.8

Program, people and quality^A

0.5

0.8

EDA, compute and design infrastructure^A

1.0

Architecture and modelling: test chip^A

1.0

Proof of concept and FPGA prototyping^A

1.0

Design and verification: test chip^D

Freeze

IP sourcing and integration: test chip^A

1.0

Physical design, DFT and sign-off: test chip^A

Freeze

Foundry and shuttle operations: test chip^A

1.0

Packaging, test and qualification: test chip^A

1.0

Bring-up, evaluation boards and validation: test chip^A

1.0^A

Firmware, software and tools: test chip^D

1.0

Architecture and modelling: product chip^A

0.3

0.5

0.8^A

Design and verification: product chip^A

0.0

0.3

0.5

IP sourcing and integration: product chip^A

0.3

0.5

0.8

Physical design, DFT and sign-off: product chip^A

0.0

0.3

0.5

Foundry and supply operations: product chip^A

0.3

0.5

0.8

Packaging, test and qualification: product chip^A

0.3

0.5

0.8

Bring-up, evaluation boards and validation: product chip^A

0.0

0.3

0.5

Firmware, software and tools: product chip^D

0.0

0.3

0.5

Key0.0Planned0.3Early draft0.5Draft0.8Evidence backed1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.You are here: Evaluation with Design PartnersAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

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Stages

Test Chip Tape-out, Bring-up & Evaluation^A
Evaluation with Design Partners (this stage)^A
Series A & Product Definition^A

Company, funding and customers milestones

Engineering milestones

Test chip sign-off (TCS)
Test chip tape-out (TT)
Test chip validated (TV) (technical readiness review TR1)
Product specification freeze (PSF)

Disciplines

Founders and company strategy^O
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.5, Draft. Build or partner choices are recorded and the company roadmap drafted, still resting on the founders' view until silicon and design partners report.
- Evaluation with Design Partners: maturity 0.8, Evidence backed. The strategy is backed by test chip results and design partner evaluations, and is the case the Series A is raised on.
- Series A & Product Definition: maturity 0.8, Evidence backed. The strategy is backed by test chip results and design partner evaluations, and is the case the Series A is raised on.
Customers and design partners^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.8, Evidence backed. Design partner interest rests on test chip results: an evaluation is signed and run, with results and intent to buy in writing.
- Evaluation with Design Partners: maturity 0.8, Evidence backed. Design partner interest rests on test chip results: an evaluation is signed and run, with results and intent to buy in writing.^A; First design partner engaged
- Series A & Product Definition: maturity 1.0, Complete. Product requirements traceable to the design partner results are accepted at the product specification freeze, and partners move on to samples.
Funding and finance^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.5, Draft. Seed money is managed against runway, with grants applied for and the Series A case outlined around the test chip.
- Evaluation with Design Partners: maturity 0.8, Evidence backed. The Series A case is backed by test chip and design partner results, and the round closes on that evidence.
- Series A & Product Definition: maturity 0.8, Evidence backed. The Series A case is backed by test chip and design partner results, and the round closes on that evidence.
Legal, IP and agreements^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.8, Evidence backed. The agreements for the test chip tape-out are signed; design partner terms are negotiated on test chip results and the product IP licences agreed with the product IP sourcing plan.
- Evaluation with Design Partners: maturity 0.8, Evidence backed. The agreements for the test chip tape-out are signed; design partner terms are negotiated on test chip results and the product IP licences agreed with the product IP sourcing plan.^A
- Series A & Product Definition: maturity 0.8, Evidence backed. The agreements for the test chip tape-out are signed; design partner terms are negotiated on test chip results and the product IP licences agreed with the product IP sourcing plan.
Program, people and quality^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.5, Draft. The test chip plan is run, with its risks tracked through tape-out and bring-up.
- Evaluation with Design Partners: maturity 0.8, Evidence backed. The product development plan is built on test chip actuals and approved with the Series A, and tape-out readiness is checked against the verification and physical sign-off reports.
- Series A & Product Definition: maturity 0.8, Evidence backed. The product development plan is built on test chip actuals and approved with the Series A, and tape-out readiness is checked against the verification and physical sign-off reports.
EDA, compute and design infrastructure^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The environment, kit and libraries carry the test chip through sign-off and tape-out and are proven on its silicon; production licences, compute and the production node design kit are then added for the product and carry it to tape-out.
- Evaluation with Design Partners: maturity 1.0, Complete. The environment, kit and libraries carry the test chip through sign-off and tape-out and are proven on its silicon; production licences, compute and the production node design kit are then added for the product and carry it to tape-out.
- Series A & Product Definition: maturity 1.0, Complete. The environment, kit and libraries carry the test chip through sign-off and tape-out and are proven on its silicon; production licences, compute and the production node design kit are then added for the product and carry it to tape-out.
Architecture and modelling: test chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The model is correlated with test chip silicon and the key claim checked; the evidence goes to the product specification.; Key claim checked on silicon
Proof of concept and FPGA prototyping^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The prototype has done its job: test chip and evaluation software are checked against the first test chip silicon, and the platform is with the software team for product firmware.
- Evaluation with Design Partners: maturity 1.0, Complete. The prototype has done its job: test chip and evaluation software are checked against the first test chip silicon, and the platform is with the software team for product firmware.
Design and verification: test chip^D
- Test Chip Tape-out, Bring-up & Evaluation: maturity Freeze, Frozen. Results: the test chip RTL is locked in the shuttle masks; silicon issues are root-caused against it in bring-up, and the lessons and the environment are kept for the product.
IP sourcing and integration: test chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The test chip IP is shown working on silicon, and the issues found are closed with the providers.
Physical design, DFT and sign-off: test chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity Freeze, Frozen. The test chip is taped out on the shuttle and its database locked; timing and power are compared with silicon in bring-up, and the correlation is ready for the product.
Foundry and shuttle operations: test chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The test chip database is delivered for the run and the test chips come back with their cost and schedule actuals.
Packaging, test and qualification: test chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The package plan is final at the tape-out, and packaged test chips are delivered and tested for evaluation.
Bring-up, evaluation boards and validation: test chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The test chip is measured, its results compared with the model and the lessons for product silicon written, and that evidence carries the evaluation kits for design partners.^A
- Evaluation with Design Partners: maturity 1.0, Complete. The test chip is measured, its results compared with the model and the lessons for product silicon written, and that evidence carries the evaluation kits for design partners.
Firmware, software and tools: test chip^D
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. Test chip and evaluation software run on silicon and with design partners.
- Evaluation with Design Partners: maturity 1.0, Complete. Test chip and evaluation software run on silicon and with design partners.
Architecture and modelling: product chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.3, Early draft. The product specification is outlined from the first test chip results and the partners' needs.
- Evaluation with Design Partners: maturity 0.5, Draft. The product specification is drafted on the correlated model, with performance targets for the production node.
- Series A & Product Definition: maturity 0.8, Evidence backed. The product specification is written and frozen on the test chip and design partner evidence.^A
Design and verification: product chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.0, Planned. Product RTL scope beyond the test chip and the design and verification team for it agreed, with effort estimated; block fixes wait for the test chip lessons.
- Evaluation with Design Partners: maturity 0.3, Early draft. Environment: the test chip blocks are fixed from the silicon lessons and the reused environment is set up for the product.
- Series A & Product Definition: maturity 0.5, Draft. Environment and first results: fixed blocks pass regression, and the product verification plan is extended to the full product scope.
IP sourcing and integration: product chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.3, Early draft. Product IP needs are drawn from the test chip and its first silicon results.
- Evaluation with Design Partners: maturity 0.5, Draft. Product IP is evaluated on the test chip evidence and candidate terms agreed.
- Series A & Product Definition: maturity 0.8, Evidence backed. The product IP sourcing plan is accepted at the product specification freeze, with licences signed or on an agreed path, and the IP deliverables are integrated into the RTL at its freeze.
Physical design, DFT and sign-off: product chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.0, Planned. Implementation effort on the production node and the changes to the shuttle flow estimated, with the team agreed; no product floorplan yet.
- Evaluation with Design Partners: maturity 0.3, Early draft. The product floorplan, die size and node are drafted from the test chip correlation.
- Series A & Product Definition: maturity 0.5, Draft. Implementation trials on the production node back the floorplan and the sign-off plan.
Foundry and supply operations: product chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.3, Early draft. Production node and supplier options are drawn up as the test chip actuals come in.
- Evaluation with Design Partners: maturity 0.5, Draft. The production node, unit cost and supply plan are built on the shuttle actuals.
- Series A & Product Definition: maturity 0.8, Evidence backed. The unit cost model and the production supply plan are agreed for the product with the Series A, and the mask and wafer order is prepared through design and sign-off for the tape-out.
Packaging, test and qualification: product chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.3, Early draft. Product package and test options are drawn from the test chip packaging experience.
- Evaluation with Design Partners: maturity 0.5, Draft. The product package and test strategy are compared against the design partners' needs.
- Series A & Product Definition: maturity 0.8, Evidence backed. The product package and test strategy are chosen at the product specification freeze, and the package design and test approach are worked out with the product RTL.
Bring-up, evaluation boards and validation: product chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.0, Planned. Product validation scope and lab needs agreed while the test chip is brought up, with the owner and effort estimated; no validation approach yet.
- Evaluation with Design Partners: maturity 0.3, Early draft. The product validation approach is drawn from the test chip lessons and the design partners' needs.
- Series A & Product Definition: maturity 0.5, Draft. The silicon validation plan and the product evaluation board are outlined against the frozen specification and RTL.
Firmware, software and tools: product chip^D
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.0, Planned. Product firmware and software development kit scope agreed from the test chip software in bring-up, with the owner and effort estimated; no plan yet.
- Evaluation with Design Partners: maturity 0.3, Early draft. Product firmware and the software development kit are planned from the evaluation software and the partners' feedback.
- Series A & Product Definition: maturity 0.5, Draft. The firmware and software development kit architecture is set against the product specification and the frozen RTL.

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