Chip lifecycle / Startup lifecycle / Test Chip Tape-out, Bring-up & Evaluation

Test Chip Tape-out, Bring-up & Evaluation

Releasing the signed-off test chip database to the multi-project wafer shuttle or small dedicated run, then packaging and bringing up the test chip on a lab board, measuring it against the model and against the claims made to investors and customers, and recording what has to change for product silicon.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^A07 Test Chip Sign-off

^A08 Test Chip Tape-out, Bring-up & EvaluationYou are here

^A09 Evaluation with Design Partners

Company, funding and customers milestones

DPSDesign partner signed PVDesign partner validation

Engineering milestones

TRFTest chip RTL freeze TCSTest chip sign-off TTTest chip tape-out TVTR1Test chip validated

Founders and company strategy^O

0.5

0.8

Customers and design partners^A

0.5

0.8

Funding and finance^A

0.5

0.8

Legal, IP and agreements^A

0.8

Program, people and quality^A

0.5

0.8

EDA, compute and design infrastructure^A

1.0

Architecture and modelling: test chip^A

0.8

1.0

Proof of concept and FPGA prototyping^A

0.8

1.0

Design and verification: test chip^D

1.0

Freeze

IP sourcing and integration: test chip^A

0.8

1.0

Physical design, DFT and sign-off: test chip^A

1.0^A

Freeze

Foundry and shuttle operations: test chip^A

0.8

1.0

Packaging, test and qualification: test chip^A

0.8

1.0

Bring-up, evaluation boards and validation: test chip^A

0.8

1.0^A

Firmware, software and tools: test chip^D

0.8

1.0

Architecture and modelling: product chip^A

0.0

0.3

0.5

Design and verification: product chip^A

0.0

0.3

IP sourcing and integration: product chip^A

0.0

0.3

0.5

Physical design, DFT and sign-off: product chip^A

0.0

0.3

Foundry and supply operations: product chip^A

0.0

0.3

0.5

Packaging, test and qualification: product chip^A

0.0

0.3

0.5

Bring-up, evaluation boards and validation: product chip^A

0.0

0.3

Firmware, software and tools: product chip^D

0.0

0.3

Key0.0Planned0.3Early draft0.5Draft0.8Evidence backed1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.You are here: Test Chip Tape-out, Bring-up & EvaluationAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

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Stages

Test Chip Sign-off^A
Test Chip Tape-out, Bring-up & Evaluation (this stage)^A
Evaluation with Design Partners^A

Company, funding and customers milestones

Engineering milestones

Test chip RTL freeze (TRF)
Test chip sign-off (TCS)
Test chip tape-out (TT)
Test chip validated (TV) (technical readiness review TR1)

Disciplines

Founders and company strategy^O
- Test Chip Sign-off: maturity 0.5, Draft. Build or partner choices are recorded and the company roadmap drafted, still resting on the founders' view until silicon and design partners report.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.5, Draft. Build or partner choices are recorded and the company roadmap drafted, still resting on the founders' view until silicon and design partners report.
- Evaluation with Design Partners: maturity 0.8, Evidence backed. The strategy is backed by test chip results and design partner evaluations, and is the case the Series A is raised on.
Customers and design partners^A
- Test Chip Sign-off: maturity 0.5, Draft. Design partner prospects are in active discussion, with the evaluation each would run outlined.

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