The whole chip, from its specification through IP integration, full-chip design and verification, tape-out, bring-up and qualification to production and end of life.
Start here: what it is, how the related terms differ, what this lifecycle covers and its phases in order, then the detail.
A system on chip, or SoC, is a single integrated circuit that brings together most of what an electronic system needs: one or more processors, on-chip memory, interfaces to external memory and peripherals, and often accelerators, analogue functions and security features. Work that once needed several chips on a board is done on one die.
Most of an SoC is assembled from IP blocks, some designed in-house and some licensed. The SoC team's own work is the architecture that ties them together, the on-chip interconnect, full-chip integration, verification, test and physical design, and the bring-up of the finished silicon with its software.
An SoC is a chip, not yet a product. The product is the SoC in its package with its datasheet, software, evaluation hardware, qualification and supply commitments.
An SoC sits between the blocks it is built from and the product and system it ends up in. From smallest to widest:
| Term | What it is | How it differs |
|---|---|---|
| IP block | A reusable design for one function.For example: A processor core or a USB controller. | One building block; an SoC integrates many. |
| Subsystem | Blocks integrated and verified together, such as a processor cluster with its caches. |
SoC and full-chip lifecycle: 15 stages, 15 gates of its own and 7 hand-offs to the Product lifecycle, from Concept & Feasibility to End of Life.
15 stages, 15 gates of its own and 7 hand-offs to the Product lifecycle, 3 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
In collaboration with The Digital Electronics Blog (opens in a new tab)
A dashed sign with a TR tag is a technical readiness review gate.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Turning an approved product idea into a chip that can be built: the main requirements, candidate architectures and their performance, the process node, critical IP and package options, with every technology risk shown feasible or given a plan at the technical readiness review before the specification is written in full.
Concept approval gate, owned by the Product lifecycle (Concept approval)TR1: Technology feasibility gateTR1, technical readiness review
Defining what the chip must do once it is shown feasible: the requirements and the architecture, written into a specification that is frozen and placed under change control.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
Specification freeze gateProduct plan agreed gate, owned by the Product lifecycle (Plan approval and development commit)
Choosing the IP blocks the chip will use, taking each release from its IP lifecycle or supplier, and connecting them into the full-chip design.
Implementing the architecture as synthesizable register-transfer-level code.
Proving the design behaves correctly through simulation, formal methods and coverage closure.
Inserting and connecting the chip's test structures around each IP block's own, and generating the patterns that test every manufactured part.
Synthesis, place-and-route, and timing/power/signal-integrity closure ahead of tape-out.
Final design hand-off to the foundry for mask generation and fabrication.
TR2: Tape-out technology readiness gateTR2, technical readiness reviewTape-out gate
Mask making and wafer fabrication at the foundry.
Die singulation, packaging, and ATE test program development and execution.
First-silicon characterization against the specification on the bench.
Engineering samples gate, owned by the Product lifecycle (Engineering samples)Silicon validated gate
Stress testing and reliability qualification (e.g.
Qualification start gateQualification passed gateTR3, technical readiness reviewProduction release gate, owned by the Product lifecycle (Production release)
Scaling volume while driving yield learning and process control.
Volume ramp gate, owned by the Product lifecycle (Volume ramp)
Steady-state manufacturing, supply management and ongoing field support.
Obsolescence management: NRND notices, last-time-buy, and EOL transition support.
Last-time buy gate, owned by the Product lifecycle (Last-time buy)Last-time ship gate, owned by the Product lifecycle (Last-time ship)Design and test data archived gate
| Larger than a block, smaller than the chip, often reused. |
| SoC | One die integrating processors, memory, interfaces and other functions. | The unit that is taped out and made. |
|---|
| ASIC | A chip designed for one customer or one application. | Says who it is for, not how much it integrates; many ASICs are SoCs. |
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| ASSP | Application specific standard product: designed for one application, sold to many customers. | Sold openly rather than to one customer. |
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| Chiplet | A die combined with other dies in one package through die-to-die links. | Splits the system across dies, which can use different processes. |
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| Die and packaged part | The silicon cut from the wafer, and that die in its package, tested. | Tape-out releases the design; the foundry, packaging and test make the part. |
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| Platform | A shared architecture, IP and software base for several SoCs. | Not one chip but the base for a family. |
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| Derivative | A new SoC built from an existing one with limited changes. | Reuses much of the design, but is taped out and qualified in its own right. |
|---|
| Product | The packaged SoC with datasheet, software, support and roadmap. | The commercial offer, managed in the product lifecycle. |
|---|
The SoC lifecycle is the engineering path of one chip, from its specification to the end of its production: deciding what it must do, designing and verifying it, taping it out, then proving, qualifying and supporting the real silicon.
It runs inside the product lifecycle, mainly in its development and validation stages, and gives the product's gates their evidence. It meets the IP lifecycle at every block it integrates.
It differs from a design flow, which lists tool steps such as synthesis, place and route and signoff. The lifecycle adds the decisions, owners and evidence at each step, and carries on through manufacturing and production.
A chip lead or programme manager usually runs it, with the SoC architect owning the technical decisions.
Gates matter here because tape-out cannot be undone. Once masks are made, a design error means new masks and a long delay. The freezes and sign-offs before tape-out exist to find problems while they are still cheap to fix.
A dotted underline opens the full definition in the glossary.
Credible sources, named for further reading. Standards are available from the body that publishes them.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.