The physical plan of the chip: where each block, memory and input or output sits, and how power and clocks are distributed.
Design data Work product in the SoC and full-chip lifecycle and the Automotive and safety-critical lifecycle
It fixes where blocks, memories, inputs and outputs sit on the die, which drives timing, power delivery and die size. A late or unreviewed floorplan meets congestion and timing problems late, grows the die and forces package and board plans to change.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.