Prototype Wafers & Characterisation

Stages

4. Process Development & Integration^A
5. Prototype Wafers & Characterisation (this stage)^D
6. Package & Module Development^A

Business and customers milestones

• Engineering samples (ES)

Device and process milestones

• Device design freeze (DDF)
• Process baseline freeze (PBF) (technical readiness review TR2)
• First wafers out (FW)
• Device characterisation complete (CC)
• Package and module design release (PDR)

Disciplines

• Power product management and business^O
  • Process Development & Integration: maturity 0.3, Concept drafted. Roadmap and target datasheet shared with lead customers while the device design and process are fixed.
  • Prototype Wafers & Characterisation: maturity 0.5, Learning. Engineering samples out with a preliminary datasheet, and customer evaluations tracked.
  • Package & Module Development: maturity 0.5, Learning. Engineering samples out with a preliminary datasheet, and customer evaluations tracked.
• Applications and system engineering^A
  • Process Development & Integration: maturity 0.5, Learning. Losses estimated for the target converters on the frozen device design, and the evaluation board concept drafted.
  • Prototype Wafers & Characterisation: maturity 0.8, Near target. Evaluation boards built and running on engineering samples, with gate drive and layout being tuned.
  • Package & Module Development: maturity 0.8, Near target. Evaluation boards built and running on engineering samples, with gate drive and layout being tuned.
• Substrate and epitaxy supply^D
  • Process Development & Integration: maturity 0.8, Near target. Epitaxy tuned with the process runs, with drift layer doping and thickness close to the device targets on the baseline.
  • Prototype Wafers & Characterisation: maturity 1.0, Complete. Material confirmed on the first wafers from the frozen baseline, with its defect baseline recorded.
  • Package & Module Development: maturity Freeze, Frozen. Specification and sources under change control; larger substrates and second sources come in as qualified changes.
• Device design and TCAD^A
  • Process Development & Integration: maturity 0.8, Near target. Cell, termination, gate and layout fixed at the design freeze and the masks ordered; the design report is updated for the process baseline.
  • Prototype Wafers & Characterisation: maturity 1.0, Complete. Design confirmed on first wafers: measured ratings correlate with the simulation, or the differences are explained.
  • Package & Module Development: maturity Freeze, Frozen. Design under change control; ruggedness and failure findings from qualification reviewed against it.
• Process development and integration^A
  • Process Development & Integration: maturity 0.8, Near target. Integrated process fixed in the frozen baseline, with critical steps capable and the process FMEA started.^A
  • Prototype Wafers & Characterisation: maturity 1.0, Complete. First wafers out on the frozen baseline, with prototype lots meeting their process targets.
  • Package & Module Development: maturity Freeze, Frozen. Baseline under change control; transfers to larger wafers and process changes are qualified before use.
• Wafer fab manufacturing and yield^A
  • Process Development & Integration: maturity 0.0, Planned. Line readiness planned for the baseline, with a first process control plan.
  • Prototype Wafers & Characterisation: maturity 0.3, Concept drafted. Prototype lots running, with a first yield and defect Pareto.
  • Package & Module Development: maturity 0.5, Learning. Sample and qualification lots running on the frozen baseline, with yield learning against material and process defects.
• Device characterisation^D
  • Process Development & Integration: maturity 0.8, Near target. Fixtures and test conditions ready and checked on test structures, with the plan ready for first wafers.
  • Prototype Wafers & Characterisation: maturity 1.0, Complete. Static, dynamic and ruggedness behaviour measured across temperature and compared with the design; repeated in the converter, on qualification lots and on larger wafers.^D
  • Package & Module Development: maturity 1.0, Complete. Static, dynamic and ruggedness behaviour measured across temperature and compared with the design; repeated in the converter, on qualification lots and on larger wafers.
• Device models and simulation support^A
  • Process Development & Integration: maturity 0.5, Learning. Pre-silicon models updated for the process baseline, ready to fit to silicon.
  • Prototype Wafers & Characterisation: maturity 0.8, Near target. Compact models fitted to silicon, and thermal network models built for the released package.^A
  • Package & Module Development: maturity 0.8, Near target. Compact models fitted to silicon, and thermal network models built for the released package.
• Reliability and ruggedness qualification^A
  • Process Development & Integration: maturity 0.5, Learning. Gate oxide and stress learning on process test structures and prototype wafers, with early results against the requirements.
  • Prototype Wafers & Characterisation: maturity 0.5, Learning. Gate oxide and stress learning on process test structures and prototype wafers, with early results against the requirements.
  • Package & Module Development: maturity 0.8, Near target. Qualification plan drafted with the package tests, and qualification lots being built on the frozen baseline.
• Package and module engineering^A
  • Process Development & Integration: maturity 0.5, Learning. Package concept and thermal path checked against the process baseline and the die size.
  • Prototype Wafers & Characterisation: maturity 0.8, Near target. Sample packages assembled for the engineering samples, with the module design under way.
  • Package & Module Development: maturity 1.0, Complete. Package or module design released with its assembly process specification and a first module datasheet for evaluation and qualification builds.^DA
• Production test and screening^A
  • Prototype Wafers & Characterisation: maturity 0.0, Planned. Sample test set up for the engineering samples, with a first test program.
  • Package & Module Development: maturity 0.3, Concept drafted. Test program extended from the characterisation report towards the qualification flow.
• Quality and automotive compliance^D
  • Process Development & Integration: maturity 0.3, Concept drafted. Design and process FMEAs under way from the design freeze to the process baseline.
  • Prototype Wafers & Characterisation: maturity 0.5, Learning. Quality plan updated with prototype and sample results, with customer-specific requirements being gathered.
  • Package & Module Development: maturity 0.5, Learning. Quality plan updated with prototype and sample results, with customer-specific requirements being gathered.
• Supply chain, capacity and cost^A
  • Process Development & Integration: maturity 0.3, Concept drafted. Capacity for prototype, sample and qualification lots planned across material, fab and assembly.
  • Prototype Wafers & Characterisation: maturity 0.3, Concept drafted. Capacity for prototype, sample and qualification lots planned across material, fab and assembly.
  • Package & Module Development: maturity 0.5, Learning. Volume capacity and cost per die modelled for the launch, with the wafer size case being prepared.