Moves the customer design into synthesis, test insertion and trial placement on the fixed base once its baseline is agreed, up to the netlist freeze. The ASIC design engineer runs it with the place-and-route lead.
MustThe converted design baseline is agreed, or for an RTL design the RTL is accepted at a tagged version.
MustThe design kit and reference flow versions for this design are locked.
MustTiming constraints are written and reviewed with the customer.
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