Marks the move into base layer tape-out and wafer banking once the base is verified, physically closed and its design kit released. The chip finishing and tape-out engineer runs it with the foundry interface manager.
MustBase array verification sign-off is reached.
MustThe base physical checks, timing and power integrity are clean or waived on the signed-off database.
ShouldThe design kit is released, so customer designs can start while the base is built.
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