Chip lifecycle / Checklists / FPGA lifecycle / Architecture and pin-out freeze: gate checklist

Architecture and pin-out freeze: gate checklist

Use to freeze the architecture, pin assignment, clocking and IP choices. Chaired by the system hardware architect with the board design lead.

1. Review set-up

MustThe evidence pack reached every participant early enough to be read before the review.
Evidence
Distribution record
Owner
Hardware design manager
MustThe people with decision rights for this gate are present or have named a delegate in writing.
Evidence
Attendance list
Owner
Hardware design manager
SeeFlow: Decision rights
MustConditions set at the previous gate are closed, or their status is reported with evidence.
Evidence
Action tracker
Owner
Hardware design manager
SeeFlow: Action and issue tracking
ShouldFPGA, board, software, verification and, where relevant, security and compliance are represented.
Evidence
Attendance list
Owner
Hardware design manager

2. Entry criteria

MustPin assignment: agreed with the board team and clean in the vendor tool's I/O and bank rule checks.
Evidence
Pin assignment and vendor rule check results
Owner
FPGA design engineer

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