Tool · Verification & Validation
Verdi
Synopsys's debug environment, originally Novas Debussy, combining waveform, source, schematic, FSM and transaction views with automated signal tracing back through the logic cone.
It is the most widely used debug tool in RTL verification.
- Also known as
- Novas Verdi, Debussy
- Type
- Tool
- Domain
- Verification & Validation, Debug
Notes
Its temporal flow and active annotation features made backtracing a failure through the design largely automatic.
Overview
Verdi is Synopsys's debug platform for chip design and verification, used to work out why a simulation or emulation run behaved as it did and to trace a failure back to its cause in the design or the testbench. It links a waveform viewer, a source code browser, state machine views and transaction-level views, so a signal can be followed from one view to another. Verdi is built around the FSDB signal database, which Synopsys describes as ubiquitous.
How it works
During simulation or emulation, signal values are dumped into an FSDB file. Verdi loads it alongside the design source, so an engineer can click on a wrong value in the waveform, jump to the code that drives it, and trace backwards through the logic and across many clock cycles to where behaviour first went wrong; Synopsys lists automatic signal tracing across many cycles and temporal flow views among its features. Testbench views, message logging and UVM transaction recording let verification engineers debug at the level of transactions as well as signals.
The platform has grown well beyond waveform debug. It includes protocol, low-power and assertion analysis, support for UPF power intent, analysis of fault simulation results and synchronised hardware and software debug that shows C and assembly code beside the hardware. A 2016 extension added unified debug of analogue and mixed-signal co-simulation, and a 2023 update added AI-driven debug that aims to tell whether a failure comes from the design or the testbench, together with regression planning and tracking through Verdi VMS.
Because debugging is labour intensive, these features aim to cut the time spent on each failure. Full visibility over long runs can produce very large dump files, so teams usually choose what to record and when.
Examples
- Tracing a wrong output value back several clock cycles to a misconnected enable in the RTL.
- Debugging a UVM testbench with transaction-level views built from transactions recorded in FSDB.
- Examining ZeBu emulation results in Verdi for high-capacity debug.
- Debugging an analogue and digital co-simulation using Verdi's mixed-signal views and annotations.
- Using regression debug automation to sort many failing tests into a smaller number of likely causes.
Why it matters
Design verification engineers, RTL designers, emulation engineers and silicon debug teams spend much of their working day in debug tools, so speed and the quality of tracing directly affect how quickly bugs are found and fixed. In a 2023 Synopsys blog, MediaTek described AI-driven regression debug in Verdi cutting root-cause analysis of regression failures from days to minutes.
Related terms
Part of the Verification & Validation glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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