VCS (Verilog Compiled Simulator)

Notes

Compiled-code simulation, which VCS popularised in the 1990s, replaced interpreted Verilog simulators on performance.

Overview

VCS is Synopsys's functional simulator for digital chip designs, used to run RTL and gate-level simulations of designs and testbenches written in SystemVerilog, Verilog, VHDL and related languages. It is one of the three main commercial logic simulators, alongside Cadence Xcelium and Siemens Questa, and is usually paired with Synopsys's Verdi debug system. The name is usually expanded as Verilog Compiled Simulator, after its origin as a simulator that compiled Verilog into native code rather than interpreting it.

How it works

VCS works in two stages. A compile step reads the design and testbench and builds a simulation executable, and a run step executes it, often thousands of times with different random seeds in a regression. The original approach, from the start-up Chronologic Simulation, was to translate Verilog into C and compile that, with the aim of speeding up RTL simulation. Viewlogic bought Chronologic in 1994, and Synopsys gained VCS when it acquired Viewlogic in 1997.

Today VCS supports the verification features of SystemVerilog, including constrained random stimulus, coverage and assertions, along with UVM testbenches. Synopsys lists features such as fine-grained parallelism to spread a simulation across processor cores, partition compile to rebuild only what changed, save and restore, X-propagation checks, low-power simulation and interfaces to SystemC and analogue simulation. Simulations can also be accelerated on Synopsys ZeBu emulation hardware.

Results are written to waveform and coverage databases and examined in Verdi, which provides waveform viewing, source browsing, UVM transaction views and regression management. Synopsys integrates VCS closely with Verdi, its VC Formal tools and its verification IP, so teams that standardise on Synopsys verification often use them together.

Examples

• A nightly UVM regression of an SoC run on VCS across a compute farm, with failures debugged the next morning in Verdi.
• A long, high-activity test sped up by allocating more processor cores at run time with fine-grained parallelism.
• An Intel success story, listed by Synopsys, that used simulation with taint propagation to reproduce a real-world security vulnerability.
• Gate-level simulation of a synthesised netlist to check reset behaviour and unknown-value propagation before tapeout.

Why it matters

Design verification engineers and RTL designers run VCS daily, while verification infrastructure and CAD teams manage its licences, versions and regressions. Simulator speed and capacity set how many tests a team can run before tapeout, so performance features and licence counts weigh heavily when companies choose between VCS, Xcelium and Questa.

In the chip lifecycle, VCS is used from block-level RTL verification through SoC regression and gate-level simulation before tapeout, and later to reproduce failures first seen in emulation, FPGA prototypes or silicon.

It matters most to: Design Verification Engineer, EDA R&D Engineer, Logic Simulation, Gate-Level Simulation Engineer, Regression Farm and Verification Infrastructure Engineer, RTL Design Engineer

Common confusions

Not the same as a version control system

In software, VCS commonly means a version control system such as Git. Chip teams use both meanings, sometimes in the same conversation.

Not the same as Xcelium or Questa

These are the competing simulators from Cadence and Siemens. They accept the same standard languages, but options, debug environments and performance differ, so testbenches do not always move between them without changes.

Related standards

• IEEE 1800 (SystemVerilog)

Sources

1. VCS: Functional Verification Solution (opens in a new tab), Synopsys, 2026-10-22
2. Verdi Automated Debug System (opens in a new tab), Synopsys, 2026-10-22
3. IEEE 1800-2023: IEEE Standard for SystemVerilog, Unified Hardware Design, Specification, and Verification Language (opens in a new tab), IEEE Standards Association, 2026-10-22
4. Chronologic Simulation (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
5. List of HDL simulators (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• Xcelium
• Questa
• Verdi
• RTL simulation

Where it appears on the Hub

Used on 23 pages of the Hub. In each group, the pages that mention it most come first.