Term · Fab Ops, Yield & Metrology
Test structure
A purpose-built pattern on a wafer, such as a transistor array, resistor chain or via chain, measured to characterise a process or monitor its health. Test structures support process development, device modelling, reliability studies and lot acceptance.
- Also known as
- Scribe-line test structure
- Type
- Term
- Domain
- Fab Ops, Yield & Metrology, Process control
Overview
A test structure is a pattern built on a wafer to be measured rather than sold, such as a single transistor, a resistor, a long chain of vias or a set of contact pads, laid out so that one property of the process can be measured cleanly. Test structures are commonly placed in the scribe lines between dies and probed during wafer parametric test. They support process development, device modelling, reliability studies and the routine check that each wafer was made correctly.
How it works
Each structure is designed to isolate one parameter. Transistors of several sizes give threshold voltage and gain; resistors and capacitors give layer resistance and dielectric properties; diodes and interconnect lines cover junctions and wiring. Some layouts follow classic measurement methods. A van der Pauw structure, a method proposed by Leo van der Pauw in 1958, uses four contacts on the edge of a thin sample to extract sheet resistance, and with a magnetic field it also gives carrier type, density and mobility. A transfer length method structure places metal pads at increasing spacing; plotting resistance against spacing gives sheet resistance from the slope and contact resistance from the intercept.
Measurements are made on a wafer prober with a dedicated probe card, at a few sites on each wafer, in wafer parametric test. This is separate from wafer sort, which runs functional patterns on every product die and uses different probe cards. Parametric results are tracked over time so that drift in the process is spotted before it costs yield.
Scribe lines cost no product area but limit the number and size of structures, so process development also uses test chips and full wafers carrying many more. The field has its own forum, the IEEE International Conference on Microelectronic Test Structures, whose roots go back to a 1979 measurement seminar. A structure only reports conditions where it sits, so its results must be read alongside data from the product dies themselves.
Examples
- A van der Pauw structure measuring the sheet resistance of a newly implanted layer.
- A transfer length method array measuring the contact resistance of a new metal contact on a compound semiconductor.
- Transistors of several gate lengths in the scribe line, measured on every lot to confirm threshold voltage stays inside its window.
- A long via chain measured after an etch change to check that no vias have opened.
Why it matters
Test structures are how a fab knows its process is in control and how designers get trustworthy models. Process integration engineers, device modelling engineers, reliability engineers and statistical process control engineers depend on their data, and wafer probe technicians run the measurements.
In the chip lifecycle, test structures are central during process development and PDK model extraction, carry reliability studies through qualification, and in volume production check every lot before wafers move on to sort.
It matters most to: Device Modeling Engineer, Process Integration Engineer, Reliability Engineer (HTOL and Wafer-Level Reliability), Statistical Process Control Engineer, Test Technician (Wafer Probe)
Common confusions
- Not the same as a test chip
- A test chip is a whole die built to evaluate a process, IP block or design idea. It may contain many test structures, but also functional circuits.
- Not the same as DFT test logic
- Scan chains and built-in self-test sit inside the product die to test its logic. Process test structures are separate patterns that measure the process itself.
Sources
- About ICMTS (opens in a new tab), IEEE International Conference on Microelectronic Test Structures, 2026-10-22
- ICMTS Archives (opens in a new tab), IEEE International Conference on Microelectronic Test Structures, 2026-10-22
- Wafer testing (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
- Van der Pauw method (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
- Transfer length method (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
Related terms
Part of the Fab Ops, Yield & Metrology glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 10 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
- Component library released (Photonics lifecycle)
- Photonic PDK & Component Libraries (Photonics lifecycle)
- Alpha PDK release (early access) (PDK lifecycle)
- Beta PDK release (design start) (PDK lifecycle)
- Design Rules & Rule Manual (PDK lifecycle)
- TR1: Material and device feasibility (Power and compound lifecycle)
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary