Test pattern

Overview

A test pattern is a set of input values applied to a chip, together with the outputs a good chip should produce, used by a tester to detect manufacturing defects or check a function. A complete test applies many such patterns in sequence. For digital logic, most patterns are now scan patterns generated automatically by ATPG tools from the design netlist and a set of fault models.

How it works

A scan pattern has three parts: values shifted into the scan chains to set the internal state, values applied at the inputs together with one or more capture clocks, and the expected values shifted out and compared on the tester. A pattern detects a fault if a chip containing that fault would give a different output from a good one. ATPG tools aim patterns at fault models, such as stuck-at faults for static defects and transition or path delay faults for timing defects, and fault simulation reports the share of modelled faults the set detects. Full stuck-at coverage alone does not guarantee quality, because bridges, opens and delay defects behave differently.

Pattern count matters because every pattern costs tester time and memory. Tools compact patterns so that each targets many faults, and on-chip compression lets a small amount of tester data fill many internal chains. Synopsys, for example, presents fewer patterns as a direct reduction in test time and cost.

Generated patterns are then translated into the form a tester needs. IEEE 1450, the Standard Test Interface Language (STIL), was written to carry digital test vectors, with their format and timing, from design tools to test equipment. Functional patterns, memory self-test and analogue tests complement the structural scan set.

Examples

• A stuck-at scan pattern set reaching high fault coverage on a large SoC.
• Transition delay patterns applied at speed to catch defects that slow a path without breaking it.
• ATPG output written in STIL so that it can be loaded onto testers from different vendors.
• Failing pattern data from wafer sort fed into diagnosis software to point failure analysis at a likely defect.

Why it matters

Patterns are the link between the DFT built into a chip and the test programme on the floor. DFT and ATPG engineers create them, test programme developers convert and debug them on the tester, and yield engineers use failing patterns for diagnosis. The pattern set largely decides how many defective parts escape, and its size sets much of the test time.

In the chip lifecycle, patterns are generated after synthesis and DFT insertion, are ready before tapeout, are debugged on first silicon, and are applied at wafer sort and final test throughout production.

It matters most to: ATE Test Program Developer, DFT Implementation Engineer, EDA R&D Engineer, DFT and ATPG, Scan Diagnosis & Yield Ramp Engineer, Test Compression Engineer

Common confusions

Not the same as test programme

The test programme is the complete software on the tester that sets power, timing and limits and runs patterns alongside parametric and analogue tests. Patterns are one part of it.

Not the same as test vector

The terms are often used interchangeably. A vector often means the values for one tester cycle, while a scan pattern spans many shift and capture cycles.

Related standards

• IEEE 1450 (STIL test pattern language)

Sources

1. IEEE 1450-2023: IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data (opens in a new tab), IEEE Standards Association, 2026-10-22
2. TestMAX ATPG: Advanced Pattern Generation (opens in a new tab), Synopsys, 2026-10-22
3. What is Design for Test (DFT)? (opens in a new tab), Synopsys, 2026-10-22
4. Automatic test pattern generation (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• ATPG
• Scan chain
• Test program

Where it appears on the Hub

Used on 6 pages of the Hub. In each group, the pages that mention it most come first.