Tool · EDA Tools & Flows
Technology file
A file in a process design kit that tells design tools about the process: its layers, their order and purpose, units, display settings and basic rules. Layout, routing and extraction tools all depend on it.
- Also known as
- Tech file
- Type
- Tool
- Domain
- EDA Tools & Flows, PDK and libraries
Overview
A technology file is the part of a process design kit that describes a manufacturing process to a design tool: which layers exist, their order in the stack, what each is for, the grid in use and how each layer looks on screen. Layout editors, routers and extraction tools read it before opening a design, so every drawn shape is tied to a real mask layer. Each tool family tends to use its own format, so one PDK usually ships several technology files.
How it works
At its core a technology file is a list of layers. Each entry names a layer, gives its numbers in the layout database and in GDSII or OASIS output, and says what kind it is: a routing metal, a via or contact cut, a well or an implant. Layers are listed in process order from the bottom up, which is how a router knows which metals a via joins. Most formats also record which layers connect, a manufacturing grid that shapes snap to, and basic width and spacing values.
The details differ by tool. The open-source Magic editor uses one text file with sections in a fixed order: planes and layer types, connectivity, mapping to GDS mask layers, and design rule and extraction sections. KLayout bundles similar data as a named technology with display settings, layer mapping, connectivity for net tracing and file options. For place and route, the technology section of a LEF file defines each routing layer's direction, pitch, width, spacing and resistance and capacitance per unit, plus vias.
Keeping these files consistent is a real maintenance task; open_pdks, for example, keeps each tool's setup in its own folder. A technology file is not the full rule set: signoff checks live in rule decks, and device models elsewhere.
Examples
- The Magic setup files for the SkyWater SKY130 process, which open_pdks installs in the PDK's libs.tech folder beside setups for KLayout and Netgen.
- A KLayout technology that gives each GDS layer a name, a display style and a place in the connectivity used by the net tracer.
- The technology section of a LEF file that tells a router the preferred direction, pitch and spacing of every metal layer.
Why it matters
PDK development engineers write and release technology files, CAD engineers install them into flows, and layout and physical design engineers rely on them daily, usually without opening them. A wrong layer number, a missing connection or a mismatched unit can give a layout that looks right on screen but writes the wrong mask data or extracts the wrong parasitics.
In the chip lifecycle, technology files arrive with the PDK before layout starts, change with each PDK release, and are used through layout, routing, extraction and stream-out at tapeout.
It matters most to: CAD / Design Methodology Engineer, Custom Layout Engineer, PDK & Design Kit Release Manager, PDK Development Engineer, Physical Design Engineer
Common confusions
- Not the same as a rule deck
- A rule deck holds the full foundry checks for a tool such as DRC or LVS. A technology file holds the layer definitions and basic values tools need to draw, route and display; some formats carry simple rules, but not the signoff set.
- Not the same as the process design kit
- The PDK is the whole package from the foundry, including device models, libraries, rule decks and documentation. The technology file is one component of it.
- Not the same as a technology node
- A technology node names a generation of manufacturing process, such as 7 nm. A technology file is a data file that describes one specific process to the tools.
Sources
- Magic Technology File Format Manual (opens in a new tab), Open Circuit Design, 2026-10-22
- Technology Management (opens in a new tab), KLayout, 2026-10-22
- Standard Cell Library/Library Exchange Format (LEF), CMPE 641 Advanced VLSI Design lecture slides (opens in a new tab), University of Maryland, Baltimore County, 2026-10-22
- open_pdks: PDK installer for open-source EDA tools (README) (opens in a new tab), FOSSi Foundation, GitHub, 2026-10-22
Related terms
Part of the EDA Tools & Flows glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 9 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary