Innovus

Notes

Succeeded the SoC Encounter line, whose command prefixes still appear in many legacy back-end scripts.

Overview

Innovus is Cadence Design Systems' digital implementation software, which turns a synthesised netlist into a floorplanned, placed, clock-balanced and routed layout ready for signoff. Cadence introduced the Innovus Implementation System in March 2015 as a fundamental overhaul of its earlier Encounter tools, and now sells it within the Innovus+ Synthesis and Implementation System, which adds RTL synthesis in the same environment. A comparable commercial system from Synopsys is Fusion Compiler, also sold as an RTL-to-GDSII solution.

How it works

Innovus is built around several core engines: GigaPlace places macros and standard cells, GigaOpt performs physical optimisation, CCOpt builds the clock tree using useful skew, and NanoRoute performs detailed routing that aims to be free of design rule violations. A typical run reads the netlist, the cell libraries and the timing constraints, then floorplans the block, places it, builds the clock tree, routes it and optimises timing, power and area at each stage.

Cadence integrates its signoff engines into the flow: Tempus for timing, Quantus for parasitic extraction, Voltus for power integrity and Pegasus for physical verification. Designers therefore see results close to signoff while they are still implementing, which reduces surprises at the end. In the Innovus+ platform, synthesis shares one database, graphical interface and Tcl or Python scripting with implementation, so a team can start from RTL or from a netlist, and an initial floorplan and power grid can be created during synthesis. Large designs are handled with multi-threading and distributed processing.

At launch Cadence claimed up to ten times faster turnaround and 10 to 20 per cent better power, performance and area than before; such figures are vendor claims. Cadence now states certification for process nodes from 130 nm to 1.4 nm, uses the OpenAccess database to exchange layout with its Virtuoso custom design environment for mixed-signal chips, and offers AI-driven optimisation and agentic AI add-ons on top of the platform.

Examples

• A 28 nm networking IP block of about 2.8 million cells that Cadence reported ran in 48 hours instead of 336 hours on eight CPUs when Innovus launched in 2015.
• A mixed-signal chip whose digital blocks are implemented in Innovus and assembled with analogue layout in Virtuoso through the shared OpenAccess database.
• An ASIC partner receiving a physically aware netlist produced with Innovus+ synthesis and completing the implementation itself.
• A design flow that uses Tempus inside Innovus for in-design timing optimisation before the final standalone timing signoff.

Why it matters

Physical design and place-and-route engineers may spend most of their working day in Innovus or a competing tool, and CAD and methodology teams build their company's implementation flows, scripts and checks around it. Which implementation tool a team uses shapes its libraries, scripts, licence budget and hiring.

In the chip lifecycle, Innovus is used for early floorplan and feasibility trials during architecture, for the main implementation work through physical design, for engineering change orders late in the project, and for handing a routed layout to signoff and physical verification before tapeout.

It matters most to: CAD / Design Methodology Engineer, EDA Physical Implementation Applications Engineer, Physical Design Engineer, Physical Design Methodology Engineer, Place-and-Route Engineer

Common confusions

Not the same as Innovus+

Innovus+ is the newer platform name that combines Innovus implementation with synthesis in one environment. Innovus on its own usually means the implementation system.

Not the same as Encounter

Encounter was Cadence's earlier digital implementation system. Innovus replaced it in 2015, but older scripts and papers still use the Encounter name.

Not the same as Tempus

Tempus is Cadence's static timing signoff tool. Innovus uses its engine during implementation, but Tempus is also run on its own for final timing signoff.

Sources

1. Innovus+ Synthesis and Implementation System (opens in a new tab), Cadence Design Systems, 2026-10-22
2. Cadence Innovus+ Synthesis and Implementation System White Paper (opens in a new tab), Cadence Design Systems, 2026-10-22
3. Tempus Timing Solution (opens in a new tab), Cadence Design Systems, 2026-10-22
4. Cadence's New Digital Implementation System: An Inside Look (Brian Fuller, 17 March 2015) (opens in a new tab), Arm Community, 2026-10-22
5. Fusion Compiler: RTL-to-GDSII Design Solution (opens in a new tab), Synopsys, 2026-10-22

Related terms

• Cadence
• Genus
• Tempus
• IC Compiler II
• DEF

Where it appears on the Hub

Used on 17 pages of the Hub. In each group, the pages that mention it most come first.